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PDF ATC35 Data sheet ( Hoja de datos )
| Número de pieza | ATC35 | |
| Descripción | Cell-based ASIC | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Comprehensive Library of Standard Logic Cells
• ATC35 I/O Cells Designed to Operate with VDD = 3.3V ± 0.3V as Main Target Operating
Conditions
• IO35 Pad Library Provides Interface to 5V Environment
• Oscillators and Phase Locked Loops for Stable Clock Sources
• Memory Cells Compiled to the Precise Requirements of the Design
• Compatible with Atmel’s Extensive Range of Microcontroller, DSP, Standard Interface
and Application Specific Cells
• High-Performance Analog Cells can be Developed on Request
Description
The Atmel ATC35 (AT56K) process is a proprietary 0.35 micron three-layer-metal
CMOS process intended for use with a supply voltage of 3.3V ± 0.3V. The following
table shows the range for which Atmel library cells have been characterized.
Table 1. Recommended Operating Conditions
Symbol
Parameter
Conditions
VDD3
VDD5
VI
VO
TEMP
DC Supply Voltage
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Operating Free Air
Temperature Range
Core and Standard I/Os
5V Interface I/Os
Industrial
Min Typ Max Unit
3.0 3.3 3.6
V
4.5 5.0 5.5
V
0
VDD
V
0
VDD
V
-55 +85 °C
The Atmel cell libraries and megacell compilers have been designed in order to be
compatible with each other. Simulation representations exist for three types of operat-
ing conditions. They correspond to three characterization conditions defined as
follows:
• MIN conditions:
TJ = -55°C
VDD (cell) = 3.60V
Process = fast (industrial best case)
• TYP conditions:
TJ = +25°C
VDD (cell) = 3.30V
Process = typ (industrial typical case)
• MAX conditions:
TJ = +100°C
VDD (cell) = 3.00V
Process = slow (industrial worst case)
Delays to tristate are defined as delay to turn off (VGS < VT) of the driving devices.
Output pad drain current corresponds to the output current of the pad when the output
voltage is VOL or VOH. The output resistor of the pad and the voltage drop due to
access resistors (in and out of the die) are taken into account. In order to have accu-
rate timing estimates, all characterization has been run on electrical netlists extracted
from the layout database.
Cell-based ASIC
ATC35
Summary
Rev. 1063CS–CBIC–01/03
1
Free Datasheet http://www.datasheet4u.net/
1 page  
Cell Matrices
1063CS–CBIC–01/03
ATC35 Summary
Table 8. CMOS Pads
CMOS Cell
Name
3-State I/O
PC3B01
•
PC3B02
•
PC3B03
•
PC3B04
•
PC3B05
•
PC3O01
PC3O02
PC3O03
PC3O04
PC3O05
PC3T01
PC3T02
PC3T03
PC3T04
PC3T05
Output Only
3-State
Output Only
•
•
•
•
•
•
•
•
•
•
Drive
Strength
1x
2x
3x
4x
5x
1x
2x
3x
4x
5x
1x
2x
3x
4x
5x
Pad Sites
Used
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 9. TTL Pads
TTL Cell
Name
3-State I/O
PT3B01
•
PT3B02
•
PT3B03
•
PT3O01
PT3O02
PT3O03
PT3T01
PT3T02
PT3T03
Output Only
3-State
Output Only
•
•
•
•
•
•
Drive
Strength
2 mA
4 mA
8 mA
2 mA
4 mA
8 mA
2 mA
4 mA
8 mA
Pad Sites
Used
1
1
1
1
1
1
1
1
1
Table 10. CMOS/TTL Input Only Pad
CMOS
Cell Name
Input Levels
Schmitt Input
Level Shifter Non-Inverting
Inverting
Pad Sites
Used
PC3D01
CMOS
•
1
PC3D11
CMOS
•1
PC3D21
CMOS
•
•
1
PC3D31
CMOS
•
•1
Note: All 3-state I/Os, 3-state output only and input pads are also available with pull-up and
pull-down device.
5
Free Datasheet http://www.datasheet4u.net/
5 Page 
Compiled FIFO
Megacells
ATC35 Summary
A compiled FIFO (first-in first-out data flow) megacell is implemented as a soft macro
built around a Dual-Port RAM.
The compiled FIFO is a buffer memory that allows access to its memory cells by two
independent ports. The read port is referred to as port A, the write port is labelled port B.
Both ports are controlled by independent clock signals and contain address counters
which are incremented during every clock cycle.
The FIFO block makes use of a compiled Dual-Port RAM with the configuration port A
read-only and port B write-only.
Number of rows: 2, ...128 in increments of 2
Number of words: 8, 16, 32, ...16384
Bits per word: 1, ...64
Total size:
8, ...16384
The word lengths of both ports may be different, but their ratio must be one of (1, 2, 4, 8,
16, 32 or 64).
The following is a list of pins which will be found on the symbol of a module:
• CKOUT is the clock input for port A (read port).
• CKIN is the clock input for port B (write port).
• DIN<0:i-1> Data input lines.
• DOUT<0:i-1> Data output lines.
• RESETZ The clear signal.
• EMPTY The empty flag.
• FULL The full flag.
• Supply (VDD) and ground (GND).
The following table shows the estimated range of performance for particular FIFO con-
figurations, without BIST, and without output load. Access time (tACC) and cycle time
(tCYC) refer to Max industrial conditions, whereas Dynamic Power dissipation refers to
typical conditions. All examples have the same configuration for both port A and port B,
with Read/Write capability. There is no additional flag.
Word Size
Word Depth
Rows x Columns
Width (mm)
Height (mm)
Access Time (tACC) (nsec)
Cycle Time (tCYC) (nsec)
Dynamic Power (mW/MHz)
4
16
8x8
0.235
0.169
2.72
4.55
0.10
8
32
16 x 16
0.307
0.227
2.91
4.86
0.15
16
64
32 x 32
0.455
0.342
3.27
5.38
0.31
32
128
64 x 64
0.724
0.573
3.97
5.89
0.80
64
256
128 x 128
1.267
1.035
5.37
7.56
2.58
1063CS–CBIC–01/03
11
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