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부품번호 | 82801GHM 기능 |
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기능 | I/O Controller Hub 7 | ||
제조업체 | Intel | ||
로고 | |||
전체 30 페이지수
Intel® I/O Controller Hub 7 (ICH7)
Family
Datasheet
— For the Intel® 82801GB ICH7, 82801GR ICH7R, 82801GDH ICH7DH,
82801GBM ICH7-M, 82801GHM ICH7-M DH, and 82801GU ICH7-U I/O
Controller Hubs
April 2007
Document Number: 307013-003
Free Datasheet http://www.datasheet4u.net/
5.1.5 Peer Cycles .......................................................................................... 102
5.1.6 PCI-to-PCI Bridge Model ........................................................................ 102
5.1.7 IDSEL to Device Number Mapping ........................................................... 103
5.1.8 Standard PCI Bus Configuration Mechanism.............................................. 103
5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5) (Desktop and Mobile Only) .......... 103
5.2.1 Interrupt Generation ............................................................................. 103
5.2.2 Power Management............................................................................... 104
5.2.2.1 S3/S4/S5 Support ................................................................... 104
5.2.2.2 Resuming from Suspended State ............................................... 104
5.2.2.3 Device Initiated PM_PME Message ............................................. 104
5.2.2.4 SMI/SCI Generation................................................................. 105
5.2.3 SERR# Generation ................................................................................ 105
5.2.4 Hot-Plug .............................................................................................. 106
5.2.4.1 Presence Detection .................................................................. 106
5.2.4.2 Message Generation ................................................................ 106
5.2.4.3 Attention Button Detection ....................................................... 107
5.2.4.4 SMI/SCI Generation................................................................. 107
5.3 LAN Controller (B1:D8:F0) (Desktop and Mobile Only) .......................................... 108
5.3.1 LAN Controller PCI Bus Interface............................................................. 108
5.3.1.1 Bus Slave Operation ................................................................ 109
5.3.1.2 CLKRUN# Signal (Mobile Only) .................................................. 110
5.3.1.3 PCI Power Management ........................................................... 110
5.3.1.4 PCI Reset Signal...................................................................... 110
5.3.1.5 Wake-Up Events...................................................................... 111
5.3.1.6 Wake on LAN* (Preboot Wake-Up) ............................................. 112
5.3.2 Serial EEPROM Interface ........................................................................ 112
5.3.3 CSMA/CD Unit ...................................................................................... 113
5.3.3.1 Full Duplex ............................................................................. 113
5.3.3.2 Flow Control ........................................................................... 113
5.3.3.3 VLAN Support ......................................................................... 113
5.3.4 Media Management Interface ................................................................. 113
5.3.5 TCO Functionality ................................................................................. 114
5.3.5.1 Advanced TCO Mode ................................................................ 114
5.4 Alert Standard Format (ASF) (Desktop and Mobile Only) ....................................... 115
5.4.1 ASF Management Solution Features/Capabilities ....................................... 116
5.4.2 ASF Hardware Support .......................................................................... 117
5.4.2.1 Intel® 82562EM/EX ................................................................. 117
5.4.2.2 EEPROM (256x16, 1 MHz) ........................................................ 117
5.4.2.3 Legacy Sensor SMBus Devices .................................................. 117
5.4.2.4 Remote Control SMBus Devices ................................................. 117
5.4.2.5 ASF Sensor SMBus Devices....................................................... 117
5.4.3 ASF Software Support ........................................................................... 118
5.5 LPC Bridge (w/ System and Management Functions) (D31:F0) ............................... 118
5.5.1 LPC Interface ....................................................................................... 118
5.5.1.1 LPC Cycle Types ...................................................................... 119
5.5.1.2 Start Field Definition ................................................................ 119
5.5.1.3 Cycle Type / Direction (CYCTYPE + DIR) ..................................... 120
5.5.1.4 SIZE...................................................................................... 120
5.5.1.5 SYNC ..................................................................................... 121
5.5.1.6 SYNC Time-Out ....................................................................... 121
5.5.1.7 SYNC Error Indication .............................................................. 121
5.5.1.8 LFRAME# Usage...................................................................... 122
5.5.1.9 I/O Cycles .............................................................................. 122
5.5.1.10 Bus Master Cycles ................................................................... 122
5.5.1.11 LPC Power Management ........................................................... 122
5.5.1.12 Configuration and Intel® ICH7 Implications................................. 123
5.5.2 SERR# Generation ................................................................................ 123
4 Intel ® ICH7 Family Datasheet
Free Datasheet http://www.datasheet4u.net/
4페이지 5.15
5.16
5.17
5.14.8.4 Active Cooling ........................................................................ 167
5.14.9 Event Input Signals and Their Usage ....................................................... 167
5.14.9.1 PWRBTN# (Power Button) ........................................................ 167
5.14.9.2 RI# (Ring Indicator)................................................................ 168
5.14.9.3 PME# (PCI Power Management Event) ....................................... 169
5.14.9.4 SYS_RESET# Signal ................................................................ 169
5.14.9.5 THRMTRIP# Signal .................................................................. 169
5.14.9.6 BM_BUSY# (Mobile/Ultra Mobile Only) ....................................... 170
5.14.10ALT Access Mode .................................................................................. 170
5.14.10.1Write Only Registers with Read Paths in ALT Access Mode ............. 171
5.14.10.2PIC Reserved Bits ................................................................... 173
5.14.10.3Read Only Registers with Write Paths in ALT Access Mode ............. 173
5.14.11System Power Supplies, Planes, and Signals ............................................ 173
5.14.11.1Power Plane Control with SLP_S3#, SLP_S4# and SLP_S5# ......... 173
5.14.11.2SLP_S4# and Suspend-To-RAM Sequencing ................................ 174
5.14.11.3PWROK Signal ........................................................................ 174
5.14.11.4CPUPWRGD Signal .................................................................. 175
5.14.11.5VRMPWRGD Signal .................................................................. 175
5.14.11.6BATLOW# (Battery Low) (Mobile/Ultra Mobile Only)..................... 175
5.14.11.7Controlling Leakage and Power Consumption during Low-Power
States ................................................................................... 175
5.14.12Clock Generators.................................................................................. 176
5.14.12.1Clock Control Signals from Intel® ICH7 to Clock
Synthesizer (Mobile/Ultra Mobile Only)....................................... 176
5.14.13Legacy Power Management Theory of Operation ....................................... 177
5.14.13.1APM Power Management (Desktop Only) .................................... 177
5.14.13.2Mobile APM Power Management (Mobile/Ultra Mobile Only) ........... 177
System Management (D31:F0).......................................................................... 178
5.15.1 Theory of Operation.............................................................................. 178
5.15.1.1 Detecting a System Lockup ...................................................... 178
5.15.1.2 Handling an Intruder ............................................................... 178
5.15.1.3 Detecting Improper Firmware Hub Programming ......................... 179
5.15.2 Heartbeat and Event Reporting via SMBus (Desktop and Mobile Only) ......... 179
IDE Controller (D31:F1) ................................................................................... 183
5.16.1 PIO Transfers ....................................................................................... 183
5.16.1.1 PIO IDE Timing Modes ............................................................. 184
5.16.1.2 IORDY Masking....................................................................... 184
5.16.1.3 PIO 32-Bit IDE Data Port Accesses ............................................ 184
5.16.1.4 PIO IDE Data Port Prefetching and Posting ................................. 185
5.16.2 Bus Master Function ............................................................................. 185
5.16.2.1 Physical Region Descriptor Format............................................. 185
5.16.2.2 Bus Master IDE Timings ........................................................... 186
5.16.2.3 Interrupts .............................................................................. 186
5.16.2.4 Bus Master IDE Operation ........................................................ 187
5.16.2.5 Error Conditions...................................................................... 188
5.16.3 Ultra ATA/100/66/33 Protocol................................................................. 188
5.16.3.1 Operation .............................................................................. 189
5.16.4 Ultra ATA/33/66/100 Timing .................................................................. 190
5.16.5 ATA Swap Bay...................................................................................... 190
5.16.6 SMI Trapping ....................................................................................... 190
SATA Host Controller (D31:F2) (Desktop and Mobile Only) .................................... 191
5.17.1 Theory of Operation.............................................................................. 192
5.17.1.1 Standard ATA Emulation .......................................................... 192
5.17.1.2 48-Bit LBA Operation............................................................... 192
5.17.2 SATA Swap Bay Support ........................................................................ 193
5.17.3 Intel® Matrix Storage Technology Configuration (Intel® ICH7R, ICH7DH,
and ICH7-M DH Only) ........................................................................... 193
Intel ® ICH7 Family Datasheet
7
Free Datasheet http://www.datasheet4u.net/
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82801GHM | I/O Controller Hub 7 | Intel |
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