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PDF HIP6302B Data sheet ( Hoja de datos )
| Número de pieza | HIP6302B | |
| Descripción | Dual Channel Synchronous Rectified Buck MOSFET Driver | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Dual Channel Synchronous Rectified
Buck MOSFET Driver
The HIP6602B is a high frequency, two power channel
MOSFET driver specifically designed to drive four power
N-Channel MOSFETs in a synchronous rectified buck
converter topology. This device is available in either a
14-lead SOIC or a 16-lead QFN package with a PAD to
thermally enhance the package. These drivers combined
with a HIP63xx or ISL65xx series of Multi-Phase Buck PWM
controllers and MOSFETs form a complete core voltage
regulator solution for advanced microprocessors.
The HIP6602B drives both upper and lower gates over a
range of 5V to 12V. This drive-voltage flexibility provides the
advantage of optimizing applications involving trade-offs
between switching losses and conduction losses.
The output drivers in the HIP6602B have the capacity to
efficiently switch power MOSFETs at high frequencies. Each
driver is capable of driving a 3000pF load with a 30ns
propagation delay and 50ns transition time. This device
implements bootstrapping on the upper gates with a single
external capacitor and resistor required for each power
channel. This reduces implementation complexity and allows
the use of higher performance, cost effective, N-Channel
MOSFETs. Adaptive shoot-through protection is integrated
to prevent both MOSFETs from conducting simultaneously.
Ordering Information
PART NUMBER
TEMP.
PKG.
RANGE (°C) PACKAGE DWG. #
HIP6602BCB
0 to 85 14 Ld SOIC M14.15
HIP6602BCB-T
14 Ld SOIC Tape and Reel
HIP6602BCBZ (Note 1)
0 to 85
14 Ld SOIC M14.15
(Pb-Free)
HIP6602BCBZ-T (Note 1) 14 Ld SOIC Tape and Reel (Pb-Free)
HIP6602BCR
0 to 85 16 Ld 5x5 QFN L16.5x5
HIP6602BCR-T
16 Ld 5x5 QFN Tape and Reel
HIP6602BCRZ (Note 1)
0 to 85
16 Ld 5x5 QFN L16.5x5
(Pb-Free)
HIP6602BCRZ-T (Note 1) 16 Ld 5x5 QFN Tape and Reel (Pb-Free)
HIP6602BCRZA (Note 1)
0 to 85
16 Ld 5x5 QFN L16.5x5
(Pb-Free)
HIP6602BCRZA-T (Note 1) 16 Ld 5x5 QFN Tape and Reel (Pb-Free)
NOTE:
1. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
July 22, 2005
HIP6602B
FN9076.5
Features
• Drives Four N-Channel MOSFETs
• Adaptive Shoot-Through Protection
• Internal Bootstrap Devices
• Supports High Switching Frequency
- Fast Output Rise Time
- Propagation Delay 30ns
• Small 14-Lead SOIC Package
• Smaller 16-Lead QFN Thermally Enhanced Package
• 5V to 12V Gate-Drive Voltages for Optimal Efficiency
• Three-State Input for Bridge Shutdown
• Supply Undervoltage Protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
Applications
• Core Voltage Supplies for Intel Pentium® III and AMD®
AthlonTM Microprocessors.
• High-Frequency, Low-Profile DC/DC Converters
• High-Current, Low-Voltage DC/DC Converters
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002-2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Free Datasheet http://www.datasheet4u.net/
1 page  
HIP6602B
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
BOOT Voltage (VBOOT - VPHASE) . . . . . . . . . . . . . . . . . . . . . . .15V
Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V
UGATE. . . . . . .VPHASE - 5V(<400ns pulse width) to VBOOT + 0.3V
VPHASE -0.3V(>400ns pulse width) to VBOOT + 0.3V
LGATE . . . . . . . . . GND - 5V(<400ns pulse width) to VPVCC + 0.3V
GND -0.3V(>400ns pulse width) to VPVCC + 0.3V
PHASE. . . . . . . . . . . . . . . . . . GND -5V(<400ns pulse width) to 15V
GND -0.3V(>400ns pulse width) to 15V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . .3kV
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . .200V
Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V ±10%
Supply Voltage Range PVCC . . . . . . . . . . . . . . . . . . . . . 5V to 12V
Thermal Information
Thermal Resistance
θJA (°C/W) θJC (°C/W)
SOIC Package (Note 2) . . . . . . . . . . . .
68
N/A
QFN Package (Note 3). . . . . . . . . . . . .
36
6
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
For Recommended soldering conditions see Tech Brief TB389.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θJC, the
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications Recommended Operating Conditions, unless otherwise specified.
PARAMETER
SYMBOL
TEST CONDITIONS
VCC SUPPLY CURRENT
Bias Supply Current
Power Supply Current
POWER-ON RESET
IVCC
IPVCC
fPWM = 500kHz, VPVCC = 12V
fPWM = 500kHz, VPVCC = 12V
VCC Rising Threshold
VCC Falling Threshold
PWM INPUT
Input Current
PWM Rising Threshold
PWM Falling Threshold
UGATE Rise Time
LGATE Rise Time
UGATE Fall Time
LGATE Fall Time
UGATE Turn-Off Propagation Delay
LGATE Turn-Off Propagation Delay
Shutdown Window
IPWM
VPWM = 0 or 5V (See Block Diagram)
VPVCC = 12V
VPVCC = 12V
TRUGATE VPVCC = VVCC = 12V, 3nF Load
TRLGATE VPVCC = VVCC = 12V, 3nF Load
TFUGATE VPVCC = VVCC = 12V, 3nF Load
TFLGATE VPVCC = VVCC = 12V, 3nF Load
TPDLUGATE VPVCC = VVCC = 12V, 3nF Load
TPDLLGATE VPVCC = VVCC = 12V, 3nF Load
Shutdown Holdoff Time
OUTPUT
Upper Drive Source Impedance
Upper Drive Sink Impedance
Lower Drive Source Current
Lower Drive Sink Impedance
RUGATE
RUGATE
ILGATE
RLGATE
VVCC = 12V, VPVCC = 5V
VVCC = VPVCC = 12V
VVCC = 12V, VPVCC = 5V
VVCC = VPVCC = 12V
VVCC = 12V, VPVCC = 5V
VVCC = VPVCC = 12V
VVCC = 12V, VPVCC = 5V or 12V
MIN TYP MAX UNITS
- 3.7 5.0 mA
- 2.0 4.0 mA
9.7 9.95 10.4
7.3 7.6 8.0
V
V
- 500 -
- 3.6 -
- 1.45 -
- 20 -
- 50 -
- 20 -
- 20 -
- 30 -
- 20 -
1.4 - 3.6
- 230 -
µA
V
V
ns
ns
ns
ns
ns
ns
V
ns
- 1.7 3.0 Ω
- 3.0 5.0 Ω
- 2.3 4.0 Ω
- 1.1 2.0 Ω
400 580
-
mA
500 730
-
mA
- 1.6 4.0 Ω
5 FN9076.5
July 22, 2005
Free Datasheet http://www.datasheet4u.net/
5 Page 
HIP6602B
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.5x5
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHB ISSUE C)
SYMBOL
A
A1
A2
A3
b
D
D1
MILLIMETERS
MIN NOMINAL MAX
0.80 0.90 1.00
- - 0.05
- - 1.00
0.20 REF
0.28 0.33 0.40
5.00 BSC
4.75 BSC
NOTES
-
-
9
9
5, 8
-
9
D2 2.55 2.70 2.85 7, 8
E
5.00 BSC
-
E1 4.75 BSC 9
E2 2.55 2.70 2.85 7, 8
e
0.80 BSC
-
k 0.25
-
--
L 0.35 0.60 0.75 8
L1 -
- 0.15 10
N 16 2
Nd 4 3
Ne 4
4
3
P-
- 0.60 9
θ-
- 12 9
Rev. 2 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
11
FN9076.5
July 22, 2005
Free Datasheet http://www.datasheet4u.net/
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet HIP6302B.PDF ] | |
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