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W49F002A 데이터시트 PDF




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부품번호 W49F002A 기능
기능 256K x 8 CMOS Flash Memory
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W49F002A 데이터시트, 핀배열, 회로
Preliminary W49F002A
256K × 8 CMOS FLASH MEMORY
GENERAL DESCRIPTION
The W49F002A is a 2-megabit, 5-volt only CMOS flash memory organized as 256K × 8 bits. The
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is
not required. The unique cell architecture of the W49F002A results in fast program/erase operations
with extremely low current consumption (compared to other comparable 5-volt flash memory products).
The device can also be programmed and erased using standard EPROM programmers.
FEATURES
Single 5-volt operations:
5-volt Read
5-volt Erase
5-volt Program
Fast program operation:
Byte-by-byte programming: 35 µS (typ.)
Fast erase operation: 100 mS (typ.)
Fast read access time: 120 nS
Ten-year data retention
Hardware data protection
One 16K byte Boot Block with Lockout
protection
Typical page write (erase/program) cycles:
10 100
Two 8K byte parameter blocks
Two main memory blocks (96K, 128K) Bytes
Low power consumption
Active current: 25 mA (typ.)
Standby current: 20 µA (typ.)
Automatic program and erase timing with
internal VPP generation
End of program or erase detection
Toggle bit
Data polling
Latched address and data
TTL compatible I/O
JEDEC standard byte-wide pinouts
Available packages: 32-pin DIP and PLCC
Publication Release Date: September 12, 2001
- 1 - Revision A1
Free Datasheet http://www.datasheet4u




W49F002A pdf, 반도체, 판매, 대치품
Preliminary W49F002A
The manufacturer and device codes may also be read via the command register; i.e., the W49F002A
is erased or programmed in a system without access to high voltage on the A9 pin. The command
sequence is illustrated in "Auto-select Codes".
Byte 0 (A0 = VIL) represents the manufacturers code (Winbond = DAh) and byte 1 (A0 = VIH) the
device identifier code (W49F002A = 0Bh). All identifiers for manufacturer and device will exhibit odd
parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the
Auto-select, A1 must be VIL.
Reset Mode: Hardware Reset
The #RESET pin provides a hardware method of resetting the device to reading array data. When the
system drives the #RESET pin low for at least a period of tRP, the device immediately terminates any
operation in progress, tri-states all data output pins, and ignores all read/write attempts for the duration
of the #RESET pulse. The device also resets the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once the device is ready to accept another
command sequence, to ensure data integrity.
Current is reduced for the duration of the #RESET pulse. When #RESET is held at VIL, the device
enters the TTL standby mode; if #RESET is held at VSS, the device enters the CMOS standby mode.
The #RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the
Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
Data Protection
The W49F002A is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device
automatically resets the internal state machine in the Read mode. Also, with its control register
architecture, alteration of the memory contents only occurs after successful completion of specific
multi-bus cycle command sequences. The device also incorporates several features to prevent
inadvertent write cycles resulting from VDD power-up and power-down transitions or system noise.
Low VDD Write Inhibit
To avoid initiation of a write cycle during VDD power-up and power-down, the W49F002A locks out
write cycles for VDD < 2.5V. When VDD < 2.5V, all internal program/erase circuits are disabled, and the
device resets to the read mode. The W49F002A ignores all writes until VDD > 2.5V. The user must
ensure that the control pins are in the correct logic state when VDD > 2.5V to prevent unintentional
writes.
Write Pulse "Glitch" Protection
Noise pulses of less than 10 nS (typical) on #OE, #OE, or #WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of #OE = VIL, #CE = VIH, or #WE = VIH. To initiate a write cycle
#CE and #WE must be a logical zero while #OE is a logical one.
Power-up Write Inhibit
Power-up of the device with #WE = #CE = VIL and #OE = VIH will not accept commands on the rising
edge of #WE. The internal state machine is automatically reset to the read mode on power-up.
-4-
Free Datasheet http://www.datasheet4u

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W49F002A 전자부품, 판매, 대치품
Preliminary W49F002A
For chip erase, the Data Polling is valid after the rising edge of the sixth pulse in the six #WE write
pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase
#WE pulse.
Just prior to the completion of Embedded Algorithm operations DQ7 may change asynchronously while
the output enable (#OE) is asserted low. This means that the device is driving status information on
DQ7 at one instant of time and then that bytes valid data at the next instant of time. Depending on
when the system samples the DQ7 output, it may read the status or valid data. Even if the device has
completed the Embedded Algorithm operations and DQ7 has a valid data, the data outputs on DQ0–
DQ6 may be still invalid. The valid data on DQ0 DQ7 will be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded
Erase Algorithm, or sector erase time-out (see "Command Definitions").
See "#DATA Polling During Embedded Algorithm Timing Diagrams".
DQ6: Toggle Bit
The W49F002A also features the "Toggle Bit" as a method to indicate to the host system that the
embedded algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (#OE toggling)
data from the device at any address will result in DQ6 toggling between one and zero. Once the
Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will
be read on the next successive attempt. During programming, the Toggle Bit is valid after the rising
edge of the fourth #WE pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid
after the rising edge of the sixth #WE pulse in the six write pulse sequence. For Sector erase, the
Toggle Bit is valid after the last rising edge of the sector erase #WE pulse. The Toggle Bit is active
during the sector erase time-out.
TABLE OF OPERATING MODES
Device Bus Operations
MODE
Read
Write
Write Inhibit
Standby
Output Disable
Reset
#CE
VIL
VIL
VIH
VIH
VIH
VIL
X
#OE
VIL
VIH
X
X
X
VIH
X
#WE
VIH
VIL
VIL
X
X
VIH
X
PIN
#RESET A0 A17
VIH Ain
VIH Ain
XX
VIH X
VIH X
VIH X
VIL X
DQ0 DQ7
Dout
Din
High Z/DOUT
High Z/DOUT
High Z
High Z
High Z
Publication Release Date: September 12, 2001
- 7 - Revision A1
Free Datasheet http://www.datasheet4u.

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부품번호상세설명 및 기능제조사
W49F002

256K X 8 CMOS FLASH MEMORY

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W49F002A

256K x 8 CMOS Flash Memory

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