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ST24FC21 데이터시트 PDF




STMicroelectronics에서 제조한 전자 부품 ST24FC21은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 ST24FC21 자료 제공

부품번호 ST24FC21 기능
기능 (ST24xx21B) 1 Kbit x8 Dual Mode Serial EEPROM
제조업체 STMicroelectronics
로고 STMicroelectronics 로고


ST24FC21 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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ST24FC21 데이터시트, 핀배열, 회로
ST24LC21B, ST24LW21
ST24FC21, ST24FC21B, ST24FW21
1 Kbit (x8) Dual Mode Serial EEPROM
for VESA PLUG & PLAY
1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
3.6V to 5.5V or 2.5V to 5.5V SINGLE SUPPLY
VOLTAGE
HARDWARE WRITE CONTROL (ST24LW21
and ST24FW21)
TTL SCHMITT-TRIGGER on VCLK INPUT
100k / 400k Hz COMPATIBILITY with the I2C
BUS BIT TRANSFER RANGE
TWO WIRE SERIAL INTERFACE I2C BUS
COMPATIBLE
I2C PAGE WRITE (up to 8 Bytes)
I2C BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
ERROR RECOVERY MECHANISM
(ST24FC21 and ST24FW21) VESA 2
COMPATIBLE
DESCRIPTION
The ST24LC21B, ST24LW21, ST24FC21,
ST24FC21B and ST24FW21 are 1K bit electrically
erasable programmable memory (EEPROM), or-
ganized in 128x8 bits. In the text, products are
referred as ST24xy21, where "x" is either "L" for
VESA 1 or "F" for VESA 2 compatible memories
and where "y" indicates the Write Control pin con-
nection: "C" means WC on pin 7 and "W" means
WC on pin 3.
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
VCC
SCL
VCLK
WC
ST24xy21
SDA
Table 1. Signal Names
SDA
SCL
Serial Data Address Input/Output
Serial Clock (I2C mode)
VCC
VSS
VCLK
Supply Voltage
Ground
Clock Transmit only mode
WC Write Control
June 2002
VSS
AI01741
Note: WC signal is only available for ST24LW21 and ST24FW21
products.
1/22
Free Datasheet http://www.datasheet4u.net/




ST24FC21 pdf, 반도체, 판매, 대치품
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Figure 3. Transmit Only Mode Waveforms
VCC
SCL
SDA
VCLK
tVPU
1
2
Bit 7
Bit 6
8 9 10 11
VCC
SCL
SDA
VCLK
Bit 6
Bit 5
Bit 4
12 13
Bit 0
17 18
Bit 7
Bit 6
19 20
AI01501
Table 4. I2C Operating Modes
Mode
ST24LC21B
RW ST24FC21
bit ST24FC21B
VCLK
Current Address
Read
’1’
X
Random Address
Read
’0’
’1’
X
X
Sequential Read
Byte Write
Page Write
Note: X = VIH or VIL
’1’
’0’
’0’
X
VIH
VIH
ST24LW21
ST24FW21
WC
X
X
X
X
VIH
VIH
Bytes
Initial Sequence
1 START, Device Select, RW = ’1’
START, Device Select, RW = ’0’, Address,
1
reSTART, Device Select, RW = ’1’
1 to 128 Similar to Current or Random Mode
1 START, Device Select, RW = ’0’
8 START, Device Select, RW = ’0’
4/22
Free Datasheet http://www.datasheet4u.net/

4페이지










ST24FC21 전자부품, 판매, 대치품
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Figure 6. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus
20
16
12
8
4
0
10
VCC
fc = 100kHz
fc = 400kHz
100
CBUS (pF)
SDA
MASTER
SCL
RL
RL
CBUS
1000
CBUS
AI01665
When the ST24FC21 (or the ST24FC21B or the
ST24FW21) first switches to the I2C mode (VESA
DDC2B mode), it enters a transition state which is
functionally identical to I2C operation. But, if the
ST24FC21 (or the ST24FC21B or the ST24FW21)
does not receive a valid I2C sequence, that is a
START condition followed by a valid Device Select
co de (10 10XXX RW f o r ST 2 4F C 21 an d
ST24FW21; 1010000 RW for ST24FC21B), within
either 128 VCLK periods or a period of time of
tRECOVERY ( appr ox imat ely 2 seconds), the
ST24FC21 (or the ST24FC21B or the ST24FW21)
will revert to the Transmit-Only mode (VESA DDC1
mode).
If the ST24FC21 (or the ST24FC21B or the
ST24FW21) decodes a valid I2C Device Select
code, it will lock into I2C mode. Under this condition,
signals applied on the VCLK input will not disturb
READ access from the ST24FC21 (or the
ST24FC21B or the ST24FW21). For WRITE ac-
cess, refer to the Signal Description paragraph.
When in the transition state, the count of VCLK
pulses and the internal 2 seconds timer are reset
by any activity on the SCL line. This means that,
after each high to low transition on SCL, the mem-
ory will re-initialise its transition state and will switch
back to Transmit-Only mode only after 128 more
VCLK pulses or after a new tRECOVERY delay.
SIGNAL DESCRIPTIONS
I2C Serial Clock (SCL). The SCL input pin is used
to synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to VCC
to act as a pull up (see Figure 6).
Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to VCC to act as pull up (see Figure 6).
Transmit Only Clock (VCLK). The VCLK input pin
is used to synchronize data out when the ST24xy21
is in Transmit Only mode.
For the ST24LC21B and the ST24FC21 or
ST24FC21B Only, the VCLK offers also a Write
Enable (active high) function when the ST24LC21B
and the ST24FC21 or ST24FC21B are in I2C bidi-
rectional mode.
Write Control (WC). An hardware Write Control
feature (WC) is offered only on ST24LW21 and
ST24FW21 on pin 3. This feature is usefull to
protect the contents of the memory from any erro-
neous erase/write cycle. The Write Control signal
is used to enable (WC = VIL) or disable (WC = VIH)
the internal write protection. When unconnected,
the WC input is internally tied to VSS by a 100k ohm
pull-down resistor and the memory is write pro-
tected.
DEVICE OPERATION
7/22
Free Datasheet http://www.datasheet4u.net/

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