PDF HX8312-A Data sheet ( Hoja de datos )

Número de pieza	HX8312-A
Descripción	144-Color TFT Controller Driver Datasheet
Fabricantes	Himax
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( DOC No. HX8312-A-DS ) HX8312-A 240 RGB x 320 dot, 262K color, with internal GRAM, TFT Mobile Single Chip Driver Version 05 March, 2006 Free Datasheet http://www.datasheet4u.net/ 1 page HX8312-A 240 RGB x 320 dot, 262K color, with internal GRAM, TFT Mobile Single Chip Driver List of Tables March, 2006 Table 2. 1 Interface Type............................................................................................................... 23 Table 2. 2 MPU selection .............................................................................................................. 24 Table 2. 3 Input bus format selection of system interface circuit ................................................... 24 Table 2. 4 Data pin function for I80 series CPU ............................................................................ 24 Table 2. 5 Data pin function for M68 series CPU .......................................................................... 24 Table 2. 6 Relation between SCLEG1-0 setting and effective edge operation of SCLK ............... 31 Table 2. 7 Bit allocation when DB17-0 used for RGB interface circuit........................................... 39 Table 2. 8 RGB Interface Mode Selection..................................................................................... 39 Table 3. 1 Display Mode Set up .................................................................................................... 42 Table 3. 2 Line Frequency Adjustment.......................................................................................... 51 Table 4. 1 X Size of Display Setting .............................................................................................. 53 Table 4. 2 Display RAM X Address and Display Panel Position ( X Size = 240 ) .......................... 53 Table 4. 3 Display RAM X Address and Display Panel Position (X Size = 208) ............................ 54 Table 4. 4 Display RAM X Address and Display Panel Position (X Size = 180) ............................ 54 Table 4. 5 Display RAM Address and Display Panel Position (X Size = 240, ADX = 0) ................ 55 Table 4. 6 X Address and Y Address Update Direction Setting ..................................................... 56 Table 5. 1 First display window area starting register 1 (R16)....................................................... 59 Table 5. 2 First display window area starting register 2 (R17)....................................................... 59 Table 5. 3 Second display window area starting register 1 (R18) ................................................. 59 Table 5. 4 Second display window starting register 2 (R19) ......................................................... 59 Table 5. 5 First display window area driving line number register 1 (R20) .................................... 59 Table 5. 6 First display window area display line number register 2 (R21) ................................... 59 Table 5. 7 Second display window area display line number register 1 (R22) .............................. 59 Table 5. 8 Second display window area display line number register 2 (R23) .............................. 59 Table 5. 9 Display Color in non-Display Areas of Partial Display Mode ........................................ 60 Table 5. 10 Gate Scan Method in non-Display Areas of Partial Display Mode.............................. 60 Table 5. 11 Partial gate register 1 (R52) ....................................................................................... 60 Table 6. 1 Scroll Area Start Register 1, 2 (R75, R76).................................................................... 62 Table 6. 2 Scroll Area Driving Line Number Register 1, 2 (R77, R78)........................................... 62 Table 6. 3 Scroll Step Number Register 1, 2 (R79, R80)............................................................... 62 Table 7. 1 Gate Line Driving Mode................................................................................................ 63 Table 8. 1 Gamma-Adjustment Registers ..................................................................................... 67 Table 8. 2 Offset, Center, Adjustment Registers ........................................................................... 69 Table 8. 3 Output Voltage of 8 to 1 Selector ................................................................................. 69 Table 8. 4 Voltage Calculation Formula ........................................................................................ 70 Table 8. 5 Voltage Calculation Formula of Grayscale Voltage....................................................... 71 Table 8. 6 Display RAM Data and Grayscale Voltage Mapping (REV = 0 D0 bit of R6)................ 72 Table 8. 7 Display RAM Data and Grayscale Voltage Mapping (REV = 1).................................... 72 Table 10. 1 Source on register (R136) .......................................................................................... 75 Table 10. 2 Gate on register (R137).............................................................................................. 75 Table 10. 3 Gate off register.......................................................................................................... 76 Table 10. 4 Control register 1 (R0)................................................................................................ 76 Table 10. 5 Gate output control register (R59) .............................................................................. 76 Table 11. 1 Scan Mode Setting ..................................................................................................... 78 Table 11. 2 Dummy line number selection register (R118)............................................................ 79 Table 11. 3 DDS pin set-up ........................................................................................................... 79 Table 12. 1 Frequency Adjustment (ROSC = 1)............................................................................ 80 Table 13. 1 Power Supply Voltage Configuration .......................................................................... 81 Table 13. 2 Power supply system control register 1 (R24)............................................................ 83 Table 13. 3 Power supply system control register 2 (R25)............................................................ 84 Table 13. 4 Power supply system control register 3 (R40)............................................................ 84 Table 13. 5 Power supply system control register 3 (R26)............................................................ 85 Table 13. 6 Power supply system control register 4 (R27)............................................................ 85 Table 13. 7 Power supply system control register 8 (R30)............................................................ 86 Table 13. 8 Power supply system control register 9 (R31)............................................................ 87 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. Subject to change without notice. -P.5- March 2006 Free Datasheet http://www.datasheet4u.net/ 5 Page HX8312-A 240 RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver Signals SDO CSTB S1~S720 G1~G321 VCOM1~4 DATA SHEET V05 Output Part I/O Pin Number Connected with Description O1 O1 O 720 O 321 O4 MPU MPU LCD LCD LCD Serial bus interface data output pin. Keep it open while using parallel bus interface Frame synchronization signal output pin. Keep it open if not in use. Source driver output pin. Output voltages to the liquid crystal. Output signals to panel gate lines. VGH: the level to select the gate lines VGL: the level not to select the gate lines VCOM output pin. They are short-circuited inside HX8312-A. Signals DB17-0 OSC2-1 C11A , C11B CX11A , CX11B C21A , C21B C22A , C22B C23A , C23B C12A , C12B Input/Output Part I/O Pin Connected Number with Description I/O 18 MPU Operates liked an 18-bit bi-directional data bus. Fix it to IOVCC or VSSD level when using serial bus interface. Don’t set MPU output as Hi-Z when MPU has no output. I/O 2 Oscillation Resistor Connect an external resistor for generating internal clock by internal R-C oscillation. Or an external clock signal is supplied through OSC1 with OSC2 open. I/O 4 Step up Connect to the step-up capacitors for step up circuit 1 operation. Leave Capacitor this pin open if the internal step-up circuit is not used. I/O 6 Step up Connect to the step-up capacitors for step up circuit 2 operation. Leave Capacitor this pin open if the internal step-up circuit is not used. I/O 2 Step up Connect to the step-up capacitors for step up circuit 3 operation. Leave Capacitor this pin open if the internal step-up circuit is not used. Signals VCC VCI IOVCC V18 RVCC VDDD VSSD VSSD2 VSSA VGH VGL ADDVDH DDVDH VCL VR2-1 VS VGLDMY Power Part I/O Pin Connected Number with Description I 1 Power supply A power supply for the internal logic circuit. VCC = 2.2 ~ 3.3V I 1 Power supply A Power supply for step-up circuit and power supply circuit. VCI = 2.5 ~ 3.3V I 1 Power supply Power supply for I/O circuit. IOVCC = 1.65 ~ 3.3V Bypass 1.8V regulator output. O 1 capacitor and V18, VDDD and RVCC must have the same voltage level. VDDD, RVCC Connect to VDDD and RVCC on the FPC. I 1 V18 and VDDD Power supply for RAM circuit. I 1 V18 and RVCC Power supply for logic circuit. I 1 System Ground Ground for digital circuit. I 1 System Ground Ground for internal circuit. I 1 System Ground Ground for analog circuit. O 1 Bypass Capacitor A positive power supply for the gate line drive circuit. O 1 Bypass Capacitor Schottky Diode A negative power supply for the gate line drive circuit. Insert a schottky diode in a forward direction to VSSA. I 1 DDVDH Power supply pins for VS and COMH regulators. Connected to DDVDH on FPC ADDVDH and O1 Bypass Output supply pin. Connected to ADVDDH on FPC. Capacitor O 1 Bypass Capacitor The voltage of Vci x (-1) output O 2 Bypass Capacitor Reference voltage output for the step-up circuit 2. O 1 Bypass Capacitor Power supply for the source drive unit. O1 - A negative power supply for the gate line drive circuit. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. Subject to change without notice. -P.11- March 2006 Free Datasheet http://www.datasheet4u.net/ 11 Page

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