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부품번호 IDT72285 기능
기능 (IDT72275 / IDT72285) CMOS SUPERSYNC FIFO
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IDT72285 데이터시트, 핀배열, 회로
CMOS SUPERSYNC FIFO™
32,768 x 18
65,536 x 18
PRELIMINARY
IDT72275
IDT72285
Integrated Device Technology, Inc.
FEATURES:
• Choose among the following memory organizations:
IDT72275
32,768 x 18
IDT72285
65,536 x 18
• Pin-compatible with the IDT72255LA/72265LA SuperSync
FIFOs
• 10ns read/write cycle time (6.5ns access time)
• Fixed, low first word data latency time
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable
settings
• Retransmit operation with fixed, low first word data
latency time
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each
flag can default to one of two preselected offsets
• Program partial flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• Independent Read and Write Clocks (permit reading and
writing simultaneously)
• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the
64-pin Slim Thin Quad Flat Pack (STQFP)
• High-performance submicron CMOS technology
DESCRIPTION:
The IDT72275/72285 are exceptionally deep, high speed,
CMOS First-In-First-Out (FIFO) memories with clocked read
and write controls. These FIFOs offer numerous improve-
ments over previous SuperSync FIFOs, including the following:
• The limitation of the frequency of one clock input with
respect to the other has been removed. The Frequency
Select pin (FS) has been removed, thus it is no longer
necessary to select which of the two clock inputs, RCLK or
WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed
and short.
• The first word data latency period, from the time the first
word is written to an empty FIFO to the time it can be read,
is now fixed and short. (The variable clock cycle counting
FUNCTIONAL BLOCK DIAGRAM
WCLK
D0 -D17
INPUT REGISTER
OFFSET REGISTER
WRITE CONTROL
LOGIC
WRITE POINTER
RAM ARRAY
32,768 x 18
65,536 x 18
RESET
LOGIC
OUTPUT REGISTER
FLAG
LOGIC
READ POINTER
FWFT/SI
READ
CONTROL
LOGIC
RCLK
Q0 -Q17
SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1998 Integrated Device Technology, Inc
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
4674 drw 01
SEPTEMBER 1998
DSC-4674/-
1
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IDT72285 pdf, 반도체, 판매, 대치품
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
D0–D17
MRS
Name
Data Inputs
Master Reset
I/O
I
I
PRS Partial Reset I
RT Retransmit
I
FWFT/SI
WCLK
First Word Fall
Through/Serial In
Write Clock
I
I
WEN
RCLK
REN
OE
SEN
LD
Write Enable
Read Clock
Read Enable
Output Enable
Serial Enable
Load
I
I
I
I
I
I
DC
FF /IR
EF /OR
PAF
PAE
HF
Q0–Q17
VCC
GND
Don't Care
I
Full Flag/
Input Ready
O
Empty Flag/
Output Ready
O
Programmable
Almost-Full Flag
O
Programmable
O
Almost-Empty Flag
Half-Full Flag
Data Outputs
Power
Ground
O
O
Description
Data inputs for a 18-bit bus.
MRS initializes the read and write pointers to zero and sets the output register to
all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT
Standard mode, one of two programmable flag default settings, and serial or
parallel programming of the offset settings.
PRS initializes the read and write pointers to zero and sets the output register to
all zeroes. During Partial Reset, the existing mode (IDT or FWFT), programming
method (serial or parallel), and programmable flag settings are all retained.
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets
the EF flag to LOW (OR to HIGH in FWFT mode) temporarily and does not disturb
the write pointer, programming method, existing timing mode or programmable flag
settings. RT is useful to reread data from the first physical location of the FIFO.
During Master Reset, selects First Word Fall Through or IDT Standard mode.
After Master Reset, this pin functions as a serial input for loading offset registers
When enabled by WEN , the rising edge of WCLK writes data into the FIFO and
offsets into the programmable registers for parallel programming, and when
enabled by SEN , the rising edge of WCLK writes one bit of data into the
programmable register for serial programming.
WEN enables WCLK for writing data into the FIFO memory and offset registers.
When enabled by REN , the rising edge of RCLK reads data from the FIFO
memory and offsets from the programmable registers.
REN enables RCLK for reading data from the FIFO memory and offset registers.
OE controls the output impedance of Qn.
SEN enables serial loading of programmable flag offsets.
During Master Reset, LD selects one of two partial flag default offsets (127 or 1,023
and determines the flag offset programming method, serial or parallel. After
Master Reset, this pin enables writing to and reading from the offset registers
This pin must be tied to either VCC or GND and must not toggle after Master
Reset.
In the IDT Standard mode, the FF function is selected. FF indicates whether or
not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR
indicates whether or not there is space available for writing to the FIFO memory.
In the IDT Standard mode, the EF function is selected. EF indicates whether or
not the FIFO memory is empty. In FWFT mode, the OR function is selected.
OR indicates whether or not there is valid data available at the outputs.
PAF goes LOW if the number of words in the FIFO memory is more than
total word capacity of the FIFO minus the full offset value m, which is stored in the
Full Offset register. There are two possible default values for m: 127 or 1,023.
PAE goes LOW if the number of words in the FIFO memory is less than offset n,
which is stored in the Empty Offset register. There are two possible default values
for n: 127 or 1,023. Other values for n can be programmed into the device.
HF indicates whether the FIFO memory is more or less than half-full.
Data outputs for an 18-bit bus.
+5 Volt power supply pins.
Ground pins.
4
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IDT72285 전자부품, 판매, 대치품
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL
THROUGH (FWFT) MODE
The IDT72275/72285 support two different timing modes
of operation: IDT Standard mode or First Word Fall Through
(FWFT) mode. The selection of which mode will operate is
determined during Master Reset, by the state of the FWFT/
SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT
Standard mode will be selected. This mode uses the Empty
Flag (EF ) to indicate whether or not there are any words
present in the FIFO. It also uses the Full Flag function (FF ) to
indicate whether or not the FIFO has any free space for
writing. In IDT Standard mode, every word read from the
FIFO, including the first, must be requested using the Read
Enable (REN ) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then
FWFT mode will be selected. This mode uses Output Ready
(OR ) to indicate whether or not there is valid data at the data
outputs (Qn). It also uses Input Ready (IR ) to indicate whether
or not the FIFO has any free space for writing. In the FWFT
mode, the first word written to an empty FIFO goes directly to
Qn after three RCLK rising edges, REN = LOW is not neces-
sary. Subsequent words must be accessed using the Read
Enable (REN ) and RCLK.
Various signals, both input and output signals operate
differently depending on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags, FF , PAF , HF , PAE , and EF
operate in the manner outlined in Table 1. To write data into to
the FIFO, Write Enable (WEN ) must be LOW. Data presented to
the DATA IN lines will be clocked into the FIFO on subsequent
transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (EF ) will go HIGH. Subsequent
writes will continue to fill up the FIFO. The Programmable
Almost-Empty flag (PAE ) will go HIGH after n + 1 words have
been loaded into the FIFO, where n is the empty offset value.
The default setting for this value is stated in the footnote of Table
1. This parameter is also user programmable. See section on
Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we
assumed no read operations were taking place, the Half-Full
flag (HF ) would toggle to LOW once the 16,385th word for
IDT72275 and 32,769th word for IDT72285 respectively was
written into the FIFO. Continuing to write data into the FIFO
will cause the Programmable Almost-Full flag (PAF ) to go
LOW. Again, if no reads are performed, the PAF will go LOW
after (32,768-m) writes for the IDT72275 and (65,536-m)
writes for the IDT72285. The offset “m” is the full offset value.
The default setting for this value is stated in the footnote of
Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
When the FIFO is full, the Full Flag (FF ) will go LOW,
inhibiting further write operations. If no reads are performed
after a reset, FF will go LOW after D writes to the FIFO.
D = 32,768 writes for the IDT72275 and 65,536 for the
IDT72285, respectively.
If the FIFO is full, the first read operation will cause FF to go
HIGH. Subsequent read operations will cause PAF and HF to
go HIGH at the conditions described in Table 1. If further read
operations occur, without write operations, PAE will go LOW
when there are n words in the FIFO, where n is the empty
offset value. Continuing read operations will cause the FIFO
to become empty. When the last word has been read from the
FIFO, the EF will go LOW inhibiting further read operations.
REN is ignored when the FIFO is empty.
When configured in IDT Standard mode, the EF and FF
outputs are double register-buffered outputs.
Relevant timing diagrams for IDT Standard mode can be
found in Figure 7, 8 and 11.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR , PAF , HF , PAE , and OR
operate in the manner outlined in Table 2. To write data into
to the FIFO, WEN must be LOW. Data presented to the DATA
IN lines will be clocked into the FIFO on subsequent transi-
tions of WCLK. After the first write is performed, the Output
Ready (OR ) flag will go LOW. Subsequent writes will continue
to fill up the FIFO. PAE will go HIGH after n + 2 words have
been loaded into the FIFO, where n is the empty offset value.
The default setting for this value is stated in the footnote of
Table 2. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we
assumed no read operations were taking place, the HF would
toggle to LOW once the 16,386th word for the IDT72275 and
32,770th word for the IDT72285, respectively was written into
the FIFO. Continuing to write data into the FIFO will cause the
PAF to go LOW. Again, if no reads are performed, the PAF will
go LOW after (32,769-m) writes for the IDT72275 and
(65,537-m) writes for the IDT72285, where m is the full offset
value. The default setting for this value is stated in the footnote
of Table 2.
When the FIFO is full, the Input Ready (IR ) flag will go HIGH,
inhibiting further write operations. If no reads are performed
after a reset, IR will go HIGH after D writes to the FIFO.
D = 32,769 writes for the IDT72275 and 65,537 writes for the
IDT72285, respectively. Note that the additional word in FWFT
mode is due to the capacity of the memory plus output register.
If the FIFO is full, the first read operation will cause the IR
flag to go LOW. Subsequent read operations will cause the
PAF and HF to go HIGH at the conditions described in Table
2. If further read operations occur, without write operations,
the PAE will go LOW when there are n + 1 words in the FIFO,
where n is the empty offset value. Continuing read operations
will cause the FIFO to become empty. When the last word has
been read from the FIFO, OR will go HIGH inhibiting further
read operations. REN is ignored when the FIFO is empty.
When configured in FWFT mode, the OR flag output is triple
register-buffered, and the IR flag output is double register-
buffered.
Relevant timing diagrams for FWFT mode can be found in
Figure 9, 10 and 12.
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IDT72285

(IDT72275 / IDT72285) CMOS SUPERSYNC FIFO

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