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KM684002AE 데이터시트 PDF




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부품번호 KM684002AE 기능
기능 512Kx8 Bit High Speed Static RAM
제조업체 Samsung
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KM684002AE 데이터시트, 핀배열, 회로
PRELIMINARY
KM684002A, KM684002AE, KM684002AI
CMOS SRAM
Document Title
512Kx8 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out.
Operated at Commercial Temperature Range.
Revision History
RevNo.
Rev. 0.0
Rev. 0.5
Rev. 1.0
Rev. 2.0
History
Initial release with Design Target.
Release to Preliminary Data Sheet.
0.1. Replace Design Target to Preliminary.
0.2. Delete 12ns part but add 17ns part.
0.3. Relax D.C and A.C parameters and insert new parameter(Icc1)
with the test condition.
0.3.1. Insert Icc1 parameter with the test condition as address is
increased with binary count.
0.3.2. Relax D.C and A.C parameters.
Items
Previous spec.
(15/ - /20ns part)
Relaxed spec.
(15/17/20ns part)
Icc
190/ - /180mA
220/215/210mA
tCW
10/ - /12ns
12/13/14ns
tAW
10/ - /12ns
12/13/14ns
tWP(OE=H)
10/ - /12ns
12/13/14ns
tWP1(OE=L)
12/ - /14ns
15/17/20ns
tDW
7/ - /9ns
8/9/10ns
Release to Final Data Sheet.
1.1. Delete Preliminary.
1.2. Delete Icc1 parameter with the test condition.
1.3. Update D.C parameters.
Items
Previous spec.
(15/17/20ns part)
Updated spec.
(15/17/20ns part)
Icc
220/215/210mA
170/165/160mA
1.4. Add the test condition for VOH1 with Vcc=5V±5% at 25°C
1.5. Add timing diagram to define tWP as ″(Timing Wave Form of
Write Cycle(CS=Low fixed)
2.1 Add extended and industrial temperature range parts.
Draft Data
Jun. 14th, 1996
Sep. 16th, 1996
Remark
Design Target
Preliminary
Jun. 5th, 1997
Final
Jun. 5th, 1997
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 2.0
February 1998
Free Datasheet http://www.datasheet-pdf.com/




KM684002AE pdf, 반도체, 판매, 대치품
KM684002A, KM684002AE, KM684002AI
PRELIMINARY
CMOS SRAM
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
NOTE: The above parameters are also guaranteed at extended and industrial temperature ranges.
Output Loads(A)
DOUT
255
+5.0V
480
30pF*
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
DOUT
255
+5.0V
480
5pF*
* Including Scope and Jig Capacitance
READ CYCLE
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power DownTime
Symbol
tRC
tAA
tCO
tOE
tLZ
tOLZ
tHZ
tOHZ
tOH
tPU
tPD
KM684002A-15
Min Max
15 -
- 15
- 15
-7
3-
0-
07
07
3-
0-
- 15
KM684002A-17
Min Max
17 -
- 17
- 17
-8
3-
0-
08
08
3-
0-
- 17
NOTE: The above parameters are also guaranteed at extended and industrial temperature ranges.
KM684002A-20
Min Max
20 -
- 20
- 20
-9
3-
0-
09
09
3-
0-
- 20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-4-
Rev 2.0
February 1998
Free Datasheet http://www.datasheet-pdf.com/

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KM684002AE 전자부품, 판매, 대치품
PRELIMINARY
KM684002A, KM684002AE, KM684002AI
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)
Address
CS
tAS(4)
tWC
tAW
tCW(3)
tWP(2)
WE
Data in
Data out
High-Z
High-Z
tLZ tWHZ(6)
tWR(5)
tDW
Valid Data
tDH
High-Z
High-Z(8)
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;
A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of
write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
FUNCTIONAL DESCRIPTION
CS WE
HX
LH
LH
LL
* NOTE : X means Dont Care.
OE
X*
H
L
X
Mode
Not Select
Output Disable
Read
Write
I/O Pin
High-Z
High-Z
DOUT
DIN
Supply Current
ISB, ISB1
ICC
ICC
ICC
-7-
Rev 2.0
February 1998
Free Datasheet http://www.datasheet-pdf.com/

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관련 데이터시트

부품번호상세설명 및 기능제조사
KM684002A

512Kx8 Bit High Speed Static RAM

Samsung
Samsung
KM684002AE

512Kx8 Bit High Speed Static RAM

Samsung
Samsung

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