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HI-8282 데이터시트 PDF




Holt Integrated Circuits에서 제조한 전자 부품 HI-8282은 전자 산업 및 응용 분야에서
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부품번호 HI-8282 기능
기능 ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER
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HI-8282 데이터시트, 핀배열, 회로
January 2001
HI-8282
GENERAL DESCRIPTION
The HI-8282 is a silicon gate CMOS device for interfacing
the ARINC 429 serial data bus to a 16-bit parallel data bus.
Two receivers and an independent transmitter are
provided. The receiver input circuitry and logic are
designed to meet the ARINC 429 specifications for loading,
level detection, timing, and protocol. The transmitter
section provides the ARINC 429 communication protocol.
Additional interface circuitry such as the Holt HI-8382 is
required to translate the 5 volt logic outputs to ARINC 429
drive levels.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The data bus interfaces with
CMOS and TTL.
Timing of all the circuitry begins with the master clock input,
CLK. For ARINC 429 applications, the master clock
frequency is 1 MHz.
Each independent receiver monitors the data stream with a
sampling rate 10 times the data rate. The sampling rate is
software selectable at either 1MHz or 125KHz. The results
of a parity check are available as the 32nd ARINC bit. The
HI-8282 examines the null and data timings and will reject
erroneous patterns. For example, with a 125 KHz clock
selection, the data frequency must be between 10.4 KHz
and 15.6 KHz.
The transmitter has a First In, First Out (FIFO) memory to
store 8 ARINC words for transmission. The data rate of the
transmitter is software selectable by dividing the master
clock, CLK, by either 10 or 80. The master clock is used to
set the timing of the ARINC transmission within the required
resolution.
APPLICATIONS
! Avionics data communication
! Serial to parallel conversion
! Parallel to serial conversion
FEATURES
! ARINC specification 429 compatible
! 16-Bit parallel data bus
! Direct receiver interface to ARINC bus
! Timing control 10 times the data rate
! Selectable data clocks
! Receiver error rejection per ARINC
specification 429
! Automatic transmitter data timing
! Self test mode
! Parity functions
! Low power, single 5 volt supply
! Industrial & full military temperature ranges
! DESC SMD part number
PIN CONFIGURATION (Top View)
N/C - 1
D/R1 - 2
D/R2 - 3
SEL - 4
EN1 - 5
EN2 - 6
BD15 - 7
BD14 - 8
BD13 - 9
BD12 - 10
BD11 - 11
HI-8282PQI
&
HI-8282PQT
33 - N/C
32 - N/C
31 - CWSTRX
30 - ENTX
29 - 429DO
28 - 429DO
27 - TX/R
26 - PL2
25 - PL1
24 - BD00
23 - BD01
44-Pin Plastic Quad Flat Pack (PQFP)
(See page 4-38 for additional Package Pin Configurations)
(DS8282 Rev. A)
HOLT INTEGRATED CIRCUITS
4-29
01/01




HI-8282 pdf, 반도체, 판매, 대치품
HI-8282
FUNCTIONAL DESCRIPTION (con't)
RECEIVER LOGIC OPERATION
3. Each data bit must follow its predecessor by not less than
8 samples and no more than 12 samples. In this manner the
bit rate is checked. With exactly 1MHz input clock frequency,
the acceptable data bit rates are as follows:
Figure 2 shows a block diagram of the logic section of each receiver.
BIT TIMING
The ARINC 429 specification contains the following timing
specification for the received data:
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSEWIDTH
HIGH SPEED LOW SPEED
100K BPS ± 1% 12K -14.5K BPS
1.5 ± 0.5 µsec 10 ± 5 µsec
1.5 ± 0.5 µsec 10 ± 5 µsec
5 µsec ± 5% 34.5 to 41.7 µsec
Again the HI-8282 accepts signals that meet these specifications
and rejects outside the tolerances. The way the logic operation
achieves this is described below:
1. Key to the performance of the timing checking logic is an ac-
curate 1MHz clock source. Less than 0.1% error is
recommmended.
2. The sampling shift registers are 10 bits long and must show
three consecutive Ones, Zeros or Nulls to be considered valid
data. Additionally, for data bits, the One or Zero in the upper bits
of the sampling shift registers must be followed by a Null in the
lower bits within the data bit time. For a Null in the word gap,
three consecutive Nulls must be found in both the upper and
lower bits of the sampling shift register. In this manner the mini-
mum pulse width is guaranteed.
DATA BIT RATE MIN
DATA BIT RATE MAX
HIGH SPEED
83K BPS
125K BPS
LOW SPEED
10.4K BPS
15.6K BPS
4. The Word Gap timer samples the Null shift register every
10 input clocks (80 for low speed) after the last data bit of a
valid reception. If the Null is present, the Word Gap counter is
incremented. A count of 3 will enable the next reception.
RECEIVER PARITY
The receiver parity circuit counts Ones received, including the
parity bit, ARINC bit 32. If the result is odd, then "0" will appear in
the 32nd bit.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates
an End of Sequence (EOS). If the receiver decoder is enabled
and the 9th and 10th ARINC bits match the control word
program bits or if the receiver decoder is disabled, then EOS
clocks the data ready flag flip flop to a "1", D/R1 or D/R2 (or both)
will go low. The data flag for a receiver will remain low until after
both ARINC bytes from that receiver are retrieved. This is
accomplished by activating EN with SEL, the byte selector, low
to retrieve the first byte and activating EN with SEL high to
retrieve the second byte. ENI retrieves data from receiver 1 and
EN2 retrieves data from receiver 2.
If another ARINC word is received, and a new EOS occurs
before the two bytes are retrieved, the data is overwritten by the
new word.
TO PINS
SEL
EN
D/R
DECODER
CONTROL
BITS
MUX
CONTROL
/ LATCH
ENABLE
CONTROL
BITS 9 & 10
32 TO 16 DRIVER
32 BIT LATCH
32 BIT SHIFT REGISTER
CONTROL
BIT BD14
DATA PARITY
CHECK
BIT CLOCK
32ND
BIT
CLOCK
OPTION
BIT
COUNTER
AND
END OF
SEQUENCE
CLOCK
CLK
EOS
EOS
ONES
NULL
SHIFT REGISTER
SHIFT REGISTER
WORD GAP
WORD GAP
TIMER
START
SEQUENCE
CONTROL
BIT CLOCK
END
ZEROS
SHIFT REGISTER
ERROR
DETECTION
ERROR
CLOCK
FIGURE 2. RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
4-32

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HI-8282 전자부품, 판매, 대치품
HI-8282
DATA BUS
PL1
PL2
TX/R
PL2
TX/R
ENTX
429DO
or
429DO
BYTE 1 VALID
tDWSET
tDWHLD
tPL
tPL12
BYTE 2 VALID
tDWSET
tDWHLD
tPL12
tPL tTX/R
tPL2EN
tENDAT
ARINC BIT
DATA
BIT 1
DATA
BIT 2
tDTX/R
DATA
BIT 32
tENTX/R
429DI
D/R
EN
SEL
PL1
PL2
TX/R
ENTX
429DO
BIT 32
tD/R
tD/REN
tSELEN
DON'T CARE
tENPL
tEN
tEND/R
tENEN
tENSEL
tPLEN
tENPL
tEN
tSELEN
DON'T CARE
tENSEL
tPLEN
tTX/REN
tTX/R
tENDAT
BIT 1
tENTX/R
tDTX/R
BIT 32
HOLT INTEGRATED CIRCUITS
4-35
tNULL

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