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AD9914 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD9914은 전자 산업 및 응용 분야에서
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부품번호 AD9914 기능
기능 3.5 GSPS Direct Digital Synthesizer
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AD9914 데이터시트, 핀배열, 회로
Data Sheet
FEATURES
3.5 GSPS internal clock speed
Integrated 12-bit DAC
Frequency tuning resolution to 190 pHz
16-bit phase tuning resolution
12-bit amplitude scaling
Programmable modulus
Automatic linear and nonlinear frequency sweeping
capability
32-bit parallel datapath interface
8 frequency/phase offset profiles
Phase noise: −128 dBc/Hz (1 kHz offset at 1396 MHz)
Wideband SFDR < −50 dBc
Serial or parallel I/O control
3.5 GSPS Direct Digital Synthesizer
with 12-Bit DAC
AD9914
1.8 V/3.3 V power supplies
Software and hardware controlled power-down
88-lead LFCSP package
PLL REF CLK multiplier
Phase modulation capability
Amplitude modulation capability
APPLICATIONS
Agile LO frequency synthesis
Programmable clock generator
FM chirp source for radar and scanning systems
Test and measurement equipment
Acousto-optic device drivers
Polar modulator
Fast frequency hopping
FUNCTIONAL BLOCK DIAGRAM
AD9914
HIGH SPEED PARALLEL
MODULATION
PORT
LINEAR
SWEEP
BLOCK
3.5GSPS DDS CORE
12-BIT DAC
REF CLK
MULTIPLIER
TIMING AND CONTROL
SERIAL OR PARALLEL
DATA PORT
Figure 1.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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AD9914 pdf, 반도체, 판매, 대치품
AD9914
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AVDD (1.8V) and DVDD (1.8V) = 1.8 V ± 5%, AVDD (3.3V) and DVDD_I/O (3.3V) = 3.3 V ± 5%, TA = 25°C, RSET = 3.3 kΩ,
IOUT = 20 mA, external reference clock frequency = 3.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted.
Table 1.
Parameter
SUPPLY VOLTAGE
DVDD_I/O
DVDD
AVDD (3.3V)
Min Typ Max
3.135
1.71
3.135
3.30
1.80
3.30
3.465
1.89
3.465
Unit
V
V
V
AVDD (1.8V)
SUPPLY CURRENT
IDVDD_I/O
IDVDD
IAVDD(3.3V)
1.71 1.80 1.89
20
433
640
V
mA
mA
mA
IAVDD(1.8V)
TOTAL POWER DISSIPATION
Base DDS Power, PLL Disabled
178
2392 3091
mA
mW
Base DDS Power, PLL Enabled
2237 2627
mW
Linear Sweep Additional Power
Modulus Additional Power
Amplitude Scaler Additional
Power
Full Power-Down Mode
28
20
138
400 616
mW
mW
mW
mW
CMOS LOGIC INPUTS
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Current (IINH, IINL)
Maximum Input Capacitance (CIN)
CMOS LOGIC OUTPUTS
Output High Voltage (VOH)
Output Low Voltage (VOL)
REF CLK INPUT CHARACTERISTICS
2.0
2.7
DVDD_I/O V
0.8 V
±60 ±200
µA
3 pF
DVDD_I/O V
0.4 V
REF CLK Multiplier Bypassed
Input Capacitance
Input Resistance
Internally Generated DC Bias
Voltage
Differential Input Voltage
REF CLK Multiplier Enabled
Input Capacitance
Input Resistance
Internally Generated DC Bias
Voltage
Differential Input Voltage
1
1.4
2
0.8 1.5
1
1.4
2
0.8 1.5
pF
V
V p-p
pF
V
V p-p
Test Conditions/Comments
Pin 16, Pin 83
Pin 6, Pin 23, Pin 73
Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52,
Pin 53, Pin 60
Pin 32, Pin 56, Pin 57
See also the total power dissipation specifications
Pin 16, Pin 83
Pin 6, Pin 23, Pin 73
Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52,
Pin 53, Pin 60
Pin 32, Pin 56, Pin 57
3.5 GHz, single-tone mode, modules disabled, linear
sweep disabled, amplitude scaler disabled
2.5 GHz, single-tone mode, modules disabled, linear
sweep disabled, amplitude scaler disabled
Manual or automatic
Using either the power-down and enable register or the
EXT_PWR_DWN pin
At VIN = 0 V and VIN = DVDD_I/O
IOH = 1 mA
IOL = 1 mA
REF CLK inputs should always be ac-coupled (both
single-ended and differential)
Single-ended, each pin
Differential
Single-ended, each pin
Differential
Rev. D | Page 4 of 48
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AD9914 전자부품, 판매, 대치품
Data Sheet
Parameter
DATA LATENCY (PIPELINE DELAY)
Single Tone Mode or Profile Mode
(Matched Latency Disabled)
Frequency
Min
Phase
Amplitude
Single Tone Mode or Profile Mode
(Matched Latency Enabled)
Frequency
Phase
Amplitude
Modulation Mode with 32-Bit Parallel
Port (Matched Latency Disabled)
Frequency
Phase
Amplitude
Modulation Mode with 32-Bit Parallel
Port (Matched Latency Enabled)
Frequency
Phase
Amplitude
Sweep Mode (Match Latency Disabled)
Frequency
Phase
Amplitude
Sweep Mode (Match Latency Enabled)
Frequency
Phase
Amplitude
Typ Max
318
342
294
318
102
318
342
318
342
342
318
342
294
318
102
AD9914
Unit Test Conditions/Comments
SYSCLK cycles = fS = system clock frequency
in GHz
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
OSK disabled
OSK enabled
OSK disabled
OSK enabled
OSK enabled
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
OSK disabled
OSK enabled
OSK disabled
OSK enabled
OSK enabled
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
OSK disabled
OSK enabled
OSK disabled
OSK enabled
OSK enabled
318
SYSCLK cycles
OSK disabled
342
SYSCLK cycles
OSK enabled
318
SYSCLK cycles
OSK disabled
342
SYSCLK cycles
OSK enabled
342
SYSCLK cycles
OSK enabled
342
SYSCLK cycles
OSK disabled
366
SYSCLK cycles
OSK enabled
318
SYSCLK cycles
OSK disabled
342
SYSCLK cycles
OSK enabled
126
SYSCLK cycles
OSK enabled
342
SYSCLK cycles
OSK disabled
366
SYSCLK cycles
OSK enabled
342
SYSCLK cycles
OSK disabled
366
SYSCLK cycles
OSK enabled
366
SYSCLK cycles
OSK enabled
Rev. D | Page 7 of 48
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