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기능 (HI-6120 / HI-6121) MIL-STD-1553 Remote Terminal ICs
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HI-6120 데이터시트, 핀배열, 회로
November, 2015
HI-6120 Parallel Bus Interface and
HI-6121 Serial Peripheral Interface (SPI)
MIL-STD-1553 Remote Terminal ICs
GENERAL DESCRIPTION
The HI-6120 and HI-6121 provide a complete, integrated,
3.3V MIL-STD-1553 Remote Terminal in a monolithic sili-
con gate CMOS device. Two host interface options are
offered: The HI-6120 uses a 16-bit parallel host bus inter-
face for access to registers and RAM and is offered in a
100-pin plastic quad flat pack (PQFP). The HI-6121 has
a 4-wire SPI (Serial Peripheral Interface) host connection
and comes in a reduced pin count 52-pin PQFP or 9mm
x 9mm 64-pin QFN. Both devices handle all aspects of
the MIL-STD-1553 protocol, including message encod-
ing, decoding, error detection, illegal command detection
and data buffering. Host data management is simplified
by storing message information and data within the on-
chip 32K x 16 static RAM.
A descriptor table in shared RAM provides fully program-
mable memory management. Multiple descriptor tables
can be implemented for fast context switching. Trans-
mit and receive commands can use any of four differ-
ent data buffer modes: indexed (single) buffering, ping-
pong (double) buffering or two circular buffer schemes.
Transmit and receive commands for each subaddress
may use different buffer modes. Mode code commands
employ a simple scheme for storing mode data and mes-
sage information with programmable interrupts.
The device provides internal illegalization capability,
allowing any subset of subaddress, command T/R bit,
broadcast vs non-broadcast and word count (or mode
code) to be illegalized, resulting in a total of 4,096 pos-
sible combinations. The illegalization table resides in in-
ternal RAM. The RT can also operate without illegal com-
mand detection, providing “in form” responses to all valid
commands. Broadcast command recognition is optional.
The HI-6120 and HI-6121 provide programmable inter-
rupts for automatic message handling, message status
and general status. A host interrupt history log maintains
information about the last 16 interrupts.
The HI-6120 and HI-6121 can be configured for automat-
ic self-initialization. A dedicated SPI port reads data from
external serial EEPROM memory to fully configure the
descriptor table, illegalization table and host interrupts.
Internal dual-redundant transceivers provide direct
connection to bus isolation transformers. The device
is offered with industrial temperature range as well as
extended temperature range with optional burn-in. A
“RoHS compliant” lead-free option is also offered.
FEATURES
Fully integrated 3.3V Remote Terminal meets all
requirements for MIL-STD-1553B Notice 2
Four data buffer modes for subaddress transmit
and receive commands. Data buffer modes are
independently selectable for transmit and receive
commands on each subaddress
• Simplified mode code command handling
Integral 16-bit Time-Tag counter has programma-
ble options for clock, interrupts and auto-synchro-
nization
Message information and time-tag words are
stored with message data words for all transacted
messages
In compliance with MIL-STD-1553B Notice 2, re-
ceived data from broadcast messages may be
optionally separated from non-broadcast received
data
Optional interrupt log buffer stores the most recent
16 interrupts to minimize host service duties
Optional illegal command detection uses internal
table
Optional automatic self-initialization at reset
±8kV ESD Protection (HBM, all pins)
MIL-STD-1760 compliant
PIN CONFIGURATION (TOP)
COMP - 1
CE - 2
MODE - 3
SI - 4
SCK - 5
SO - 6
MCLK - 7
RTA0 - 8
RTA1 - 9
RTA2 - 10
MR - 11
RTA3 - 12
RTA4 - 13
HI-6121PQx
HI-6121 in
PQFP-52 Package
39 - TEST
38 - LOCK
37 - MTSTOFF
36 - BUSA
35 - VCCP
34 - BUSA
33 - BUSB
32 - VCCP
31 - BUSB
30 - TEST0
29 - TEST3
28 - TEST2
27 - TEST1
DS6120 Rev. I
HOLT INTEGRATED CIRCUITS
www.holtic.com
1
11/15




HI-6120 pdf, 반도체, 판매, 대치품
HI-6120, HI-6121
5.14. Time-Tag Utility Register (0x0011)............................................................................ 39
5.15. Bus A Select Register (0x0012)................................................................................. 40
5.16. Bus B Select Register (0x0013)................................................................................ 40
5.17. Built-in Test Word Register (0x0014)......................................................................... 40
5.18. Alternate Built-in Test Word Register (0x0015)......................................................... 42
5.19. Reserved Register (0x0016)..................................................................................... 42
5.20. Test Control Register (0x0017) ................................................................................. 42
5.21. Loopback Test Transmit Data Register (0x0018)...................................................... 46
5.22. Loopback Test Receive Data Register (0x0019)....................................................... 46
6. COMMAND RESPONSES................................................................................ 47
6.1. RT to RT Commands. ................................................................................................. 48
7. COMMAND ILLEGALIZATION TABLE.............................................................. 49
8. TEMPORARY RECEIVE DATA BUFFER.......................................................... 53
9. INTERRUPT LOG BUFFER.............................................................................. 53
10. DESCRIPTOR TABLE....................................................................................... 56
10.1. Receive Subaddress Control Word............................................................................. 58
10.2. Transmit Subaddress Control Word............................................................................ 61
10.3. Data Buffer Options for Mode Code Commands......................................................... 63
10.4. Receive Mode Command Control Word...................................................................... 64
10.5. Transmit Mode Command Control Word..................................................................... 66
11. MESSAGE DATA BUFFERS............................................................................. 70
11.1. Subaddress Message Information Words .................................................................. 71
11.1.1. Receive Subaddress Command ................................................................................. 71
11.1.2. Transmit Subaddress Command ................................................................................ 73
11.2. Mode Command Message Information Words............................................................ 74
11.2.1. Receive Mode Command ........................................................................................... 75
11.2.2. Transmit Mode Command ........................................................................................... 76
11.3. Ping-Pong Data Buffering............................................................................................ 79
11.3.1. Double Buffered (Ping-Pong) Mode............................................................................. 79
11.3.2. Ping-Pong Enable / Disable Handshake...................................................................... 80
11.3.3. Broadcast Message Handling in Ping-Pong Mode...................................................... 82
11.4. Indexed Data Buffer Mode........................................................................................... 84
11.4.1. Single Message Mode................................................................................................. 84
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HI-6120 전자부품, 판매, 대치품
HI-6120, HI-6121
List of Figures
Figure 1.  HI-6120 / HI-6121 Block Diagram................................................................................. 10
Figure 2.  Address Mapping for Registers and RAM..................................................................... 19
Figure 3.  MIL-STD-1553 Command Word Structure.................................................................... 47
Figure 4.  Deriving the Illegalization Table Address From the Received Command Word............ 50
Figure 5.  Fixed Address Mapping for Illegalization Table ............................................................ 51
Figure 6.  Summary of Illegalization Table Addresses for Mode Code Commands....................... 52
Figure 7.  Fixed Address Mapping for Interrupt Log Buffer ........................................................... 55
Figure 8.  Address Mapping for Descriptor Table .......................................................................... 57
Figure 9.  Deriving a Descriptor Table Control Word Address From Command Word .................. 58
Figure 10.  Illustration of Ping-Pong Buffer Mode ......................................................................... 81
Figure 11.  Ping-Pong Buffer Mode Example for a Receive Subaddress ..................................... 83
Figure 12.  Illustration of Indexed Buffer Mode ............................................................................. 86
Figure 13.  Indexed Buffer Mode Example for a Receive Subaddress (broadcast not enabled) .. 87
Figure 14.  Illustration of Circular Buffer Mode 1........................................................................... 90
Figure 15.  Circular Buffer Mode 1 Example for a Receive Subaddress ...................................... 91
Figure 16.  Illustration of Circular Buffer Mode 2........................................................................... 95
Figure 17.  Circular Buffer Mode 2 Example for a Receive Subaddress ...................................... 96
Figure 18.  Generalized Single-Byte Transfer Using SPI Protocol.
SCK is Shown for SPI Modes 0 and 3 .......................................................................111
Figure 19.  Single-Word (2-Byte) Read From RAM or a Register................................................113
Figure 20.  Single-Word (2-Byte) Write To RAM or a Register.....................................................113
Figure 21.  HI-6121 Host Bus Interface Timing Diagram............................................................. 149
Figure 22.  Register and RAM Write Operations for BTYPE = 1................................................. 150
Figure 23.  Register and RAM Write Operations for BTYPE = 0................................................. 151
Figure 24.  Register and RAM Read Operations for BTYPE = 1................................................. 152
Figure 25.  Register and RAM Read Operations for BTYPE = 0................................................. 153
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부품번호상세설명 및 기능제조사
HI-6120

(HI-6120 / HI-6121) MIL-STD-1553 Remote Terminal ICs

Holt Integrated Circuits
Holt Integrated Circuits
HI-6121

(HI-6120 / HI-6121) MIL-STD-1553 Remote Terminal ICs

Holt Integrated Circuits
Holt Integrated Circuits

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