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PDF ICS95V842 Data sheet ( Hoja de datos )
| Número de pieza | ICS95V842 | |
| Descripción | DDR Phase Lock Loop Clock Driver | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS95V842
DDR Phase Lock Loop Clock Driver (60MHz - 220MHz)
Recommended Application:
1:2 DDRI Clock Driver
Product Description/Features:
• Low skew, low jitter PLL clock driver
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• With bypass mode mux
• Operating frequency 60 to 220 MHz
Switching Characteristics:
• CYCLE - CYCLE jitter: <75ps
• OUTPUT - OUTPUT skew: <60ps
• Period jitter: ±75ps
• Half-Period jitter: ±75ps
Pin Configuration
VDD2.5 1
DDRT0 2
DDRC0 3
GND 4
CLK_INT 5
CLK_INC 6
AVDD 7
AGND 8
16 GND
15 DDRC1
14 DDRT1
13 VDD2.5
12 FB_INC
11 FB_INT
10 FB_OUTT
9 FB_OUTC
16 pin SSOP
Functionality
INPUTS
OUTPUTS
PLL State
AVDD CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC
GND
L
H LH L
H Bypassed/Off
GND H
L HL H
L Bypassed/Off
2.5V
(nom)
L
H LH L
H
On
2.5V
(nom)
H
L HL H
L
On
Block Diagram
FB_INT
FB_INC
CLK_INC
CLK_INT
PLL
FB_OUTT
FB_OUTC
DDRT (1:0)
DDRC(1:0)
AVDD
0830A—09/10/04
Free Datasheet http://www.nDatasheet.com
1 page  
ICS95V842
Switching Characteristics
TA = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
MIN TYP
Max clock frequency3
freqop
40
Application Frequency
Range3
freqApp
60
Input clock duty cycle
Input clock slew rate
dtin
tsl(I)
40
1
CLK stabilization
Low-to high level propagation
delay time
TSTAB
tPLH1
CLK_IN to any output
High-to low level propagation
delay time
tPHL1
CLK_IN to any output
Output enable time
ten PD# to any output
5
Output disable time
Period jitter
Half-period jitter
tdis
tjit (per)
tjit(hper)
PD# to any output
5
-75
-75
Output clock slew rate
Cycle to Cycle Jitter
tsl(o)
tcyc-tcyc
Over the application
frequency range
1
-75
Static Phase Offset
t(spo)
-50
Output to Output Skew
tskew
40
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=twH/tc,
were the cycle (tc) decreases as the frequency goes up.
3. Switching characteristics are guaranteed for application frequency range. The
PLL Locks over the Max Clock Frequency range, but the device doe not
necessarily meet other timing parameters.
4. Does not include jitter.
MAX UNITS
333 MHz
220 MHz
60 %
2 v/ns
100 µs
5.5 ns
5.5 ns
ns
ns
75 ps
75 ps
2.5 v/ns
75 ps
50 ps
60 ps
0830A—09/10/04
5
Free Datasheet http://www.nDatasheet.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet ICS95V842.PDF ] | |
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