PDF ICS95V860 Data sheet ( Hoja de datos )

Número de pieza	ICS95V860
Descripción	2.5V DDR/Zero Delay Fan Out Buffer
Fabricantes	Integrated Circuit Systems
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No Preview Available ! Integrated Circuit Systems, Inc. ICS95V8 6 0 2.5V DDR/Zero Delay Fan Out Buffer (100MHz - 225MHz) Recommended Application: DDR Memory Modules / Zero Delay Fan Out Buffer Product Description/Features: • Low skew, low jitter PLL clock driver • 1 to 13 differential clock distribution (SSTL_2) • Feedback pins for input to output synchronization • PD# for power management • Spread Spectrum-tolerant inputs • Auto PD when input signal removed • 0°C to 85°C operation Functionality INPUTS AVDD PD# CLK_INT OUTPUTS CLK_INC CLKT CLKC FB_OUTT FB_OUTC PLL State GND H L H LH L H Bypassed/off GND 2.5V (nom) 2.5V (nom) 2.5V (nom) 2.5V (nom) H L H H X HL XX LH HL <20MHz) HL ZZ LH HL ZZ H Z L H Z L Bypassed/off Z off H on L on Z off Switching Characteristics: • CYCLE - CYCLE jitter (>100MHz):<75ps • OUTPUT - OUTPUT skew: <70ps • DUTY CYCLE: 49% - 51% Block Diagram PD# I2C_SCL, I2C_SDA I2C_A0, I2CA1 Control Logic FB_INT FB_INC CLK_INC CLK_INT PLL 0675D—01/07/04 FB_OUTT FB_OUTC CLKT0 CLKC0 CLKT1 CLKC1 CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 CLKT5 CLKC5 CLKT6 CLKC6 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9 CLKT10 CLKC10 CLKT11 CLKC11 CLKT12 CLKC12 Free Datasheet http://www.nDatasheet.com 1 page ICS95V8 6 0 Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Current IIH VI = VDD or GND 5 µA Input Low Current IIL VI = VDD or GND 5 µA Operating Supply Current High Impedance Output Current IDD2.5 IDDPD IOZ CL = 0pf @ 200MHz Enable = Low, FIN = 0 MHz VDD = 2.7V, Vout=VDD or GND 250 290 200 ±10 mA µA µA Input Clamp Voltage VIK VDDQ = 2.3V Iin = -18mA -1.2 V High-level output voltage VOH IOH = -1 mA IOH = -12 mA VDD - 0.1 1.7V V V Low-level output voltage VOL IOL=1 mA IOL=12 mA Input Capacitance4 CIN VI = GND or VDD 0.1 V 0.6 V 2.5 3.5 pF Supply Voltage VDDQ, AVDD 2.3 2.7 V I2C Supply Voltage VDD_I2C I2C VDD supply pin 2.3 3.6 V Low level input voltage VIL CLKT, CLKC, FB_INC PD#, I2C_A0, I2C_A1 VDDQ/2 - 0.18 V -0.3 0.7 V VIL_I2C I2C_SDA, I2C_SCL -0.3 0.3 x VDD_I2C V High level input voltage CLKT, CLKC, FB_INC VIH PD# VDDQ/2 + 0.18 1.7 VDDQ + 0.6 V V VIH_I2C I2C_SDA, I2C_SCL 0.7 x VDD_I2C VDD_I2C + 0.6 V DC input signal voltage2 -0.3 VDDQ V Differential input signal voltage3 DC - CLKT, FB_INT VID AC - CLKT, FB_INT Output differential cross- voltage VOX Input differential cross- voltage VIX High level output current IOH VOH = 1.7V 0.36 0.7 VDDQ/2 - 0.15 VDDQ/2 - 0.2 VDDQ + 0.6 VDDQ + 0.6 VDDQ/2 + 0.15 V V V VDDQ/2 + 0.2 V -12 mA Low level output current IOL VOL = 0.6V 12 mA Input slew rate Operating free-air temperature SR TA 1 0 Notes: 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VT-VC] required for switching, where VT is the true input level and VC is the complementary input level. 4. Guaranteed by design, not 100% tested in production. 0675D—01/07/04 4 V/ns 85 °C 5 Free Datasheet http://www.nDatasheet.com 5 Page

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