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ADP7142 데이터시트 PDF




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부품번호 ADP7142 기능
기능 CMOS LDO
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ADP7142 데이터시트, 핀배열, 회로
Preliminary Technical Data
40 V, 200 mA, Low Noise, CMOS LDO
ADP7142
FEATURES
Low Noise: 11 µVRMS independent of fixed output voltage
PSRR of 83 dB @ 10 KHz, 68 dB @ 100 KHz, 50 dB @ 1 MHz,
VOUT ≤5V, VIN = 7V
Input voltage range: 2.7 V to 40 V
Maximum output current: 200 mA
Low dropout voltage: 200 mV @ 200 mA load, VOUT = 5V
Initial accuracy: ±1%
Accuracy over line, load, and temperature: ±2%
User programmable Soft Start (LFCSP and SOIC only)
Low Quiescent Current, IGND = 50 μA with no load
Low shutdown current: 1.5 μA @ VIN = 5 V, 3μA @ VIN = 40 V
Stable with small 2.2µF ceramic output capacitor
16 fixed output voltage options: 1.2V to 5.0V
Adjustable output from 1.2 V to VIN - VDO
Output may be adjusted above initial set point
Precision Enable
2x2mm, 6-lead LFCSP package, 8-Lead SOIC, 5-Lead TSOT
APPLICATIONS
Regulation to noise sensitive applications: ADC, DAC circuits,
Precision amplifiers, Power for VCO Vtune control
Communications and Infrastructure
Medical and Healthcare
Industrial and Instrumentation
GENERAL DESCRIPTION
The ADP7142 is a CMOS, low dropout linear regulator that
operates from 2.7 V to 40 V and provide up to 200 mA of output
current. These high input voltage LDOs are ideal for regulation of
high performance analog and mixed signal circuits operating from
40 V down to 1.2 V rails. Using an advanced proprietary
architecture, they provide high power supply rejection, low noise,
and achieve excellent line and load transient response with just a
small 2.2 µF ceramic output capacitor.
The ADP7142 is available in 16 fixed output voltage options. Each
fixed output voltage may be adjusted above the initial set point with
an external feedback divider. This allows the ADP7142 to provide
TYPICAL APPLICATION CIRCUITS
VIN=6V
CIN
2.2uF
VIN
VOUT
Sense/Adj
On
Off
SS
EN
GND
VOUT=5V
COUT
2.2uF
CSS
1nF
Figure 1. ADP7142 with Fixed Output Voltage, 5 V
VIN=7V
CIN
2.2uF
VIN
VOUT
Sense/Adj
VOUT=6V
2K
On
Off
SS 10K
EN
GND
CSS
1nF
Figure 2. ADP7142 with 5V Output Adjusted to 6 V
COUT
2.2uF
an output voltage from 1.2 V to VOUT - VDO with high PSRR and
low noise.
User programmable soft start with an external capacitor is available
in the LFCSP and SOIC packages.
The ADP7142 regulator output noise is 11 μVrms independent of
the output voltage for the fixed options of 5V or less. The
ADP7142 is available in a 6-lead, 2 mm × 2 mm LFCSP making
them not only very compact solutions, but also providing excellent
thermal performance for applications requiring up to 200 mA of
output current in a small, low-profile footprint. The ADP7142 is
also available in a 5-lead TSOT and an 8-lead SOIC.
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2014 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.Datasheet4U.com




ADP7142 pdf, 반도체, 판매, 대치품
ADP7142
Preliminary Technical Data
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Parameter
Symbol Conditions
Min Typ Max Unit
Minimum Input and Output
Capacitance1
CMIN TA = −40°C to +125°C
1.5 µF
Capacitor ESR
RESR TA = −40°C to +125°C
0.001
0.3 Ω
1 The minimum input and output capacitance should be greater than 1.5 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. PrD | Page 4 of 25
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ADP7142 전자부품, 판매, 대치품
Preliminary Technical Data
ADP7142
SOIC
8
EP
TSOT
1
2
3
4
5
Mnemonic
VIN
EP
Mnemonic
VIN
GND
EN
SENSE/ADJ
VOUT
Description
Regulator Input Supply. Bypass VIN to GND with a 2.2 µF or greater capacitor.
Exposed pad on the bottom of the package. EP enhances thermal performance and is electrically
connected to GND inside the package. It is recommended that the EP connect to the ground plane on
the board.
Description
Regulator Input Supply. Bypass VIN to GND with a 2.2 µF or greater capacitor.
Ground.
Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup,
connect EN to VIN.
Sense input. Connect to load. An external resistor divider may also be used to set the output voltage
higher than the fixed output voltage
Regulated Output Voltage. Bypass VOUT to GND with a 2.2 µF or greater capacitor.
Rev. PrD | Page 7 of 25
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ADP7142

CMOS LDO

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