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부품번호 | CYUSB3326 기능 |
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기능 | (CYUSB330x - CYUSB332x) HX3 USB 3.0 Hub | ||
제조업체 | Cypress Semiconductor | ||
로고 | |||
전체 30 페이지수
CYUSB330x
CYUSB331x
CYUSB332x
HX3 USB 3.0 Hub
General Description
HX3 is a family of USB 3.0 hub controllers compliant with the USB 3.0 specification revision 1.0. HX3 supports SuperSpeed (SS),
Hi-Speed (HS), Full-Speed (FS), and Low-Speed (LS) on all the ports. It has integrated termination, pull-up, and pull-down resistors,
and supports configuration options through pin-straps to reduce the overall BOM of the system.
HX3 includes the following Cypress-proprietary features:
Shared Link™: Enables extra downstream (DS) ports for on-board connections in embedded applications
Ghost Charge™: Enables charging of devices connected to the DS ports when no host is connected on the upstream (US) port
HX3 USB 3.0 Hub
Features
USB 3.0-Certified Hub, TID# 330000047
Supports up to Four USB 3.0-Compliant DS ports
■ All ports support SS (5 Gbps), and are backward-compatible
with HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps)
■ SS and USB 2.0 Link Power Management (LPM)
■ Dedicated Hi-Speed Transaction Translators (Multi-TT)
■ LED status indicators – suspend, SS, and USB 2.0 operation
Shared Link™ for Embedded Applications
■ Each DS port can simultaneously connect to an embedded SS
device and a removable USB 2.0 device
■ Enables up to eight device connections
Enhanced Battery Charging
■ Each DS port complies with the USB Battery Charging v1.2
(BC v1.2) specification
■ Ghost Charge™: Each DS port can emulate a Dedicated
Charging Port (DCP) when the host is not connected to the US
port
■ Accessory Charger Adapter Dock (ACA-Dock): Enables
charging and simultaneous data transfer for a smart phone or
a tablet acting as a host compliant to BC v1.2
■ Apple charging supported on all DS ports
Integrated ARM® Cortex™-M0 CPU
■ 16 KB RAM, 32 KB ROM
■ Configure GPIOs for overcurrent protection, power enable, and
LEDs
■ Upgrade firmware using (a) I2C EEPROM or (b) an external
I2C master
Vendor-Command Support to Implement a USB-to-I2C
Bridge
■ Firmware upgrade of an external ASSP connected to HX3
through USB
■ In-System Programming (ISP) of the EEPROM connected to
HX3 through USB
Extensive Configuration Support
■ Pin-strap configuration for the following functions:
❐ Vendor ID (VID)
❐ Charging support for each DS port
❐ Number of active ports
❐ Number of non-removable devices
❐ Ganged or individual power switch enables for DS ports
❐ Power switch polarity selection
■ Custom configuration modes supported with eFuse, I2C
EEPROM, or I2C slave
❐ SS and USB 2.0 PHY parameters
❐ Product ID (PID)/VID, manufacturer, and product string
descriptors
❐ Swap DP/DM signals for flexible PCB routing
Software Features
■ Microsoft WHQL-certified for Windows XP/Vista/7/8/8.1
■ Compatible with Mac OS 10.9 and Linux kernel version 3.11
■ Customize configuration parameters with the easy-to-use
Cypress’s “Blaster Plus” software tool
Flexible Packaging Options
■ 68-pin QFN (8 × 8 × 1.0 mm)
■ 88-pin QFN (10 × 10 × 1.0 mm)
■ Industrial temperature range (–40 °C to +85 °C)
Errata: For information on silicon errata, see Errata on page 30. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-73643 Rev. *F
• San Jose, CA 95134-1709 • +1-408-943-2600
Revised February 25, 2014
Free Datasheet http://www.0PDF.com
CYUSB330x
CYUSB331x
CYUSB332x
Architecture Overview
The Block Diagram on page 2 shows the HX3 architecture. HX3
consists of two independent hub controllers (SS and USB 2.0),
the Cortex-M0 CPU subsystem, an I2C interface, and port
controller blocks.
SS Hub Controller
This block supports the SS hub functionality based on the
USB 3.0 specification. The SS hub controller supports the
following:
■ SS link power management (U0, U1, U2, U3 states)
■ Full-duplex data transmission
USB 2.0 Hub Controller
This block supports the LS, FS, and HS hub functionalities. It
includes the repeater, frame timer, and four transaction trans-
lators.
The USB 2.0 hub controller block supports the following:
■ USB 2.0 link power management (L0, L1, L2, L3 states)
■ Suspend, resume, and remote wake-up signaling
■ Multi-TT (one TT for each DS port)
CPU
The ARM Cortex-M0 CPU subsystem is used for the following
functions:
■ System configuration and initialization
■ Battery charging control
■ Vendor-specific commands for the USB-to-I2C bridge
■ String-descriptor support
■ Suspend status indicator
■ Shared Link support in embedded systems
I2C Interface
The I2C interface in HX3 supports the following:
■ I2C Slave, Master, and Multi-master configurations
❐ Configure HX3 by an external I2C master in I2C slave mode
❐ Configure HX3 from an I2C EEPROM
❐ Multi-master mode to share EEPROM with other I2C masters
■ In-System Programming of the I2C EEPROM from HX3’s
US port
Port Controller
The port controller block controls DS port power to comply with
the BC v1.2 and USB 3.0 specifications. This block also controls
the US port power in the ACA-Dock mode. Control signals for
external power switches are implemented within the chip. HX3
controls the external power switches at power-on to reduce
in-rush current.
The port controller block supports the following:
■ Overcurrent detection
■ SS and USB 2.0 port indicators for each DS port
■ Ganged and individual power control modes
■ Automatic port numbering based on active ports
Applications
■ Standalone hubs
■ PC and tablet motherboards
■ Docking station
■ Hand-held cradles
■ Monitors
■ Digital TVs
■ Set-top boxes
■ Printers
Table 1. HX3 Product Options
Features
Number of DS
ports
Number of
Shared Link ports
BC v1.2
ACA-Dock
External Power
Switch Control
Pin-Strap support
I2C
Vendor command
Port indicators
Packages
Temperature
range
CYUSB3302
2 (USB 3.0)
0
Yes
No
Ganged
No
Yes
Yes
No
68-QFN
Industrial and
Commercial
CYUSB3304
4 (USB 3.0)
0
Yes
No
Ganged
No
Yes
Yes
No
68-QFN
Industrial and
Commercial
CYUSB3312
2 (USB 3.0)
0
Yes
No
Individual and
Ganged
Yes
Yes
Yes
Yes
88-QFN
Industrial and
Commercial
CYUSB3314
4 (USB 3.0)
0
CYUSB3326
6 (2 USB 3.0,
2 SS, 2 USB 2.0)
2
CYUSB3328
8 (4 SS,
4 USB 2.0)
4
Yes
No
Individual and
Ganged
Yes
Yes
Yes
Yes
88-QFN
Industrial and
Commercial
Yes
No
Individual
Yes
Yes
Yes
No
88-QFN
Industrial and
Commercial
Yes
Yes
Individual
Yes
Yes
Yes
No
88-QFN
Industrial and
Commercial
Document Number: 001-73643 Rev. *F
Page 4 of 33
Free Datasheet http://www.0PDF.com
4페이지 Pin Information
Figure 6. HX3 68-Pin QFN 2-Port Pinout
CYUSB330x
CYUSB331x
CYUSB332x
DVDD12 1
RREF_USB2 2
DVDD12 3
AVDD33
US_TXM
4
5
US_TXP 6
DVDD12 7
US_RXM 8
US_RXP 9
AVDD12 10
NC 11
NC 12
DVDD12 13
NC 14
NC 15
AVDD12 16
VBUS_US 17
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
68-Pin QFN
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
51 DS1_RXP
50 DS1_RXM
49 DVDD12
48 DS1_TXM
47 DS1_TXP
46 AVDD12
45 DS2_RXP
44 DS2_RXM
43 DVDD12
42 DS2_TXM
41 DS2_TXP
40 GND
39 NC
38 NC
37 DVDD12
36 NC
35 NC
Document Number: 001-73643 Rev. *F
Page 7 of 33
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부품번호 | 상세설명 및 기능 | 제조사 |
CYUSB3324 | HX3 USB 3.0 Hub | Cypress Semiconductor |
CYUSB3326 | (CYUSB330x - CYUSB332x) HX3 USB 3.0 Hub | Cypress Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |