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부품번호 | AW6688 기능 |
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기능 | Stand-Alone Ethernet Controller | ||
제조업체 | AWINIC | ||
로고 | |||
AW6688 Datasheet
December 2011 V1.0
Stand-Alone Ethernet Controller
FEATURES
5X5 mm, 32-pin QFN
Compatible with Motorola SPI SPEC
Input clock frequency up to 60MHz
Only support phase 0
Only support polarity 0
IEEE 802.3 compatible Ethernet controller
Fully compatible with 10/100 BASE-T
networks
Integrated MAC and 10/100 PHY
Supports full and half duplex modes
Programmable padding and CRC
generation
Programmable padding and CRC stripping
Programmable flow control
Supports Ethernet frame length up to
1522 bytes
Flexible address filtering modes
8k byte receive buffer
4k byte transmit buffer
Multi-function LED output
2.8V IO supply and 1.2V core supply
CMOS process technology
The AW6688 adopts TRQ5x5-32L package:
INTR 25
GND_D 26
VCC12D 27
NC 28
NC 29
TE 30
NC 31
GND_D 32
AW6688
33
GND_A
16 CKO
15 LED1
14 LED0
13 RSTN
12 NC
11 NC
10 NC
9 GND_A
Copyright© 2008 by AWINIC Technology Co. Ltd.
Page 1 of 24
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AW6688 Datasheet
December 2011 V1.0
3 OVERVIEW
AW6688 is a standalone SPI to Ethernet converter which serves as an Ethernet network
interface for any controller with SPI master interface. The SPI interface is fully compatible with
MOTO SPI interface SPEC and only supports phase 0 and polarity 0 of the SPI clock. The clock
rate of the SPI interface is up to 60MHz. A dedicated interrupt output is used to communicate
with the SPI master chip. The Ethernet interface of AW6688 is fully compatible with IEEE802.3
protocol. A number of embedded filters are used to limit the incoming Ethernet packets.
Integrated hardware CRC calculator helps to release the CPU power of the master. A 4k byte
transmit buffer and an 8k byte receive buffer is integrated. Stream mode of transferring the
Ethernet packets through the SPI interface is supports under which the SPI transfer boundary
can be at any word boundary of the Ethernet packets. The block diagram of the chip is shown
below.
Figure 1 AW6688 block diagram
spi_if
spi_if_top
tx_fifo
rx_fifo
spi_reg
Frame
dec
clk & rst
rx data fifo
tx data fifo
tx stat fifo
Reg interface
MAC PHY
The function of the major block of AW6688 is listed below:
SPI_IF: the SPI_IF serves as the SPI protocol decoder and serial to parallel converter.
TX_FIFO, RX_FIFO: the FIFO servers as the synchronizer between the SPI clock domain and
the system clock domain.
FRAME_DEC: the FRAME_DEC decodes and encodes the SPI packet, performs the register
programming, recognizes the Ethernet packets and performs the data transfer between
the internal data FIFO.
SPI_REG: all the SPI related registers and the interrupt related logic are implemented in
the SPI_REG
MAC: the MAC implements the IEEE802.3 compliant MAC logic.
PHY: the PHY performs the data transfer between the analog interface and the MAC.
Copyright© 2008 by AWINIC Technology Co. Ltd.
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4페이지 AW6688 Datasheet
December 2011 V1.0
5 EXTERNAL CONNECTIONS
5.1 Oscillator
AW6688 is designed to operate at 25MHz with an external crystal connected to XTAL_P and
XTAL_N, To comply with IEEE 802.3 Ethernet timing requirements, the clock must have no more
than ±50 ppm of total error;
When clocking the device using a crystal, follow the connections shown in the following figure.
When using a CMOS clock oscillator or other external clock source, please connect the clock
source directly to pin XTAL_P, and leave XTAL_N open.
5.2 Ethernet signal pins
Typical applications for AW6688 devices require an Ethernet transformer module, and a few
resistors and capacitors to implement a complete IEEE 802.3 compliant 10/100 Ethernet
interface, as shown in the following figure
For cost reduction purpose, following transformerless circuit also works with degraded signal
quality.
Copyright© 2008 by AWINIC Technology Co. Ltd.
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