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PDF NT5CB128M16HP Data sheet ( Hoja de datos )
| Número de pieza | NT5CB128M16HP | |
| Descripción | 2Gb DDR3 SDRAM H-Die | |
| Fabricantes | Nanya | |
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2Gb DDR3 SDRAM H-Die
NT5CB128M16HP
NT5CC128M16HP
Feature
1.35V -0.067V/+0.1V & 1.5V ± 0.075V (JEDEC
Standard Power Supply)
8 Internal memory banks (BA0- BA2)
Differential clock input (CK, )
Programmable Latency: 5, 6, 7, 8, 9, 10,
11, 12, 13 and 14
WRITE Latency (CWL): 5,6,7,8,9 and 10
POSTED CAS ADDITIVE Programmable Additive
Latency (AL): 0, CL-1, CL-2 clock
Programmable Sequential / Interleave Burst Type
Programmable Burst Length: 4, 8
8n-bit prefetch architecture
Output Driver Impedance Control
Through ZQ pin (RZQ:240 ohm±1%)
Differential bidirectional data strobe
Internal(self) calibration:Internal self calibration
OCD Calibration
Dynamic ODT (Rtt_Nom & Rtt_WR)
Auto Self-Refresh
Self-Refresh Temperature
RoHS Compliance and Halogen free
Packages:
96-Balls BGA for x16 components
Operating temperature
Commerical grade (0℃≦TC≦95℃)
For -BE,-CG,-DI, -EK, -FL
Industrial grade (-40℃≦TC≦95℃)
For -CGI,-DII
REV 1.4
02 /2013
1
© NANYA TECHNOLOGY CORP.
All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Free Datasheet http://www.0PDF.com
1 page  
2Gb DDR3 SDRAM H-Die
NT5CB128M16HP
NT5CC128M16HP
NANYA Component Part Numbering Guide
NT 5C C 128M16 H P
DI
NANYA
Technology
Product Family
5S = SDRAM
5D = DDR SDRAM
5T = DDR2 SDRAM
5C = DDR3 SDRAM
Interface & Power( VDD& VDDQ )
V = LVTTL (3.3V , 3.3V)
E = LVTTL (2.5V , 2.5V)
S = SSTL_2 (2.5V , 2.5V)
M = LVTTL (1.8V , 1.8V)
U = SSTL_ 18 (1.8V , 1.8V)
B = SSTL_ 15 (1.5V , 1.5V)
A = SSTL_ 18 (2.0V , 2.0V)
C = SSTL_135 (1.35V , 1.35V)
F = SSTL_125 (1.25V ,1..25V)
Organization(Depth , Width)
4M 16 = 8M 8 = 64 Mb
8M 16 = 16M 8 = 128Mb
16M 16 = 32M 8 = 64M 4 = 256Mb
32M 16 = 64M 8 = 128M 4 = 512Mb
64M 16 = 128M 8 = 256M 4 = 1Gb
128M 16 = 256M 8 = 512M 4 = 2Gb
256M 16 = 512M 8 = 1024M4 = 4Gb
Note: M= Mono
Device Version
A = 1st Version B = 2nd Version
C = 3rd Version D = 4th Version
E = 5th Version F = 6th Version
G = 7th Version H = 8th Version
Special Type Option
I = Industrial Temp
B = Reduced Standby
Speed
SDRAM
75B = PC-133 3-3-3
6K = PC-166 3-3-3
DDR SDRAM
6K = DDR - 333 2.5-3-3
5T = DDR - 400 3-3-3
DDR2 SDRAM
5A = DDR2 - 400 3-3-3
37B = DDR2 - 533 4-4-4
3C = DDR2 - 667 5-5-5
25C/AC = DDR2 - 800 5-5-5
25D/AD = DDR2 - 800 6-6-6
BE = DDR2-1066 7-7-7
BD = DDR2-1066 6-6-6
DDR 3 SDRAM
AC = DDR3 - 800 5-5-5
AD = DDR3 - 800 6-6-6
BE = DDR3 - 1066 7-7-7
BF = DDR3 - 1066 8-8-8
CF = DDR3- 1333 8-8-8
CG = DDR3- 1333 9-9-9
DG = DDR3- 1600 9-9-9
DH = DDR3- 1600 10-10-10
DI = DDR3- 1600 11-11-11
EJ = DDR3- 1866 12-12-12
EK = DDR3- 1866 13-13-13
FK = DDR3- 2133 13-13-13
Package Code
RoHS + Halogen Free
S= TSOP(II )
N=78 -Ball BGA
P=96 -Ball BGA
E=60 -Ball BGA
J=68 -Ball BGA
M=92 -Ball BGA
U=71 -Ball BGA
Y=63 -Ball BGA
8=136-Ball BGA
G= DDR1 BGA / DDR2 84- Ball BGA
REV 1.4
02 /2013
5
© NANYA TECHNOLOGY CORP.
All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Free Datasheet http://www.0PDF.com
5 Page 
2Gb DDR3 SDRAM H-Die
NT5CB128M16HP
NT5CC128M16HP
Basic Functionality
The DDR3(L) SDRAM H-Die is a high-speed dynamic random access memory internally configured as an eight-bank
DRAM. The DDR3(L) SDRAM uses an 8n prefetch architecture to achieve high speed operation. The 8n prefetch
architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write operation for the DDR3(L) SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal
DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.
Read and write operation to the DDR3(L) SDRAM are burst oriented, start at a selected location, and continue for a burst
length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration of an Active
command, which is then followed by a Read or Write command. The address bits registered coincident with the Active
command are used to select the bank and row to be activated (BA0-BA2 select the bank; A0-A13 select the row). The
address bit registered coincident with the Read or Write command are used to select the starting column location for the
burst operation, determine if the auto precharge command is to be issued (via A10), and select BC4 or BL8 mode ‘on the
fly’ (via A12) if enabled in the mode register.
Prior to normal operation, the DDR3(L) SDRAM must be powered up and initialized in a predefined manner. The following
sections provide detailed information covering device reset and initialization, register definition, command descriptions
and device operation.
RESET and Initialization Procedure
Power-up Initialization sequence
The Following sequence is required for POWER UP and Initialization
1. Apply power ( is recommended to be maintained below 0.2 x VDD, all other inputs may be undefined).
needs to be maintained for minimum 200μs with stable power. CKE is pulled “Low” anytime before being
de-asserted (min. time 10ns). The power voltage ramp time between 300mV to VDDmin must be no greater than 200ms;
and during the ramp, VDD>VDDQ and (VDD-VDDQ) <0.3 Volts.
- VDD and VDDQ are driven from a single power converter output, AND
- The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one
side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to 0.95V max once
power ramp is finished, AND
- Vref tracks VDDQ/2.
OR
- Apply VDD without any slope reversal before or at the same time as VDDQ.
- Apply VDDQ without any slope reversal before or at the same time as VTT & Vref.
- The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one
side and must be larger than or equal to VSSQ and VSS on the other side.
2. After is de-asserted, wait for another 500us until CKE become active. During this time, the DRAM will start
internal state initialization; this will be done independently of external clocks.
3. Clock (CK, ) need to be started and stabilized for at least 10ns or 5tCK (which is larger) before CKE goes active.
Since CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be meeting. Also a NOP or
Deselect command must be registered (with tIS set up time to clock) before CKE goes active. Once the CKE registered
“High” after Reset, CKE needs to be continuously registered “High” until the initialization sequence is finished,
including expiration of tDLLK and tZQinit.
11
REV 1.4
02 /2013
© NANYA TECHNOLOGY CORP.
All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Free Datasheet http://www.0PDF.com
11 Page | ||
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