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D64084 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 D64084
기능 UPD64084
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D64084 데이터시트, 핀배열, 회로
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD64084
THREE-DIMENSIONAL Y/C SEPARATION LSI WITH ON-CHIP MEMORY
DESCRIPTION
The µPD64084 realizes a high precision Y/C separation by the three-dimension signal processing for NTSC signal.
This product has the on-chip 4-Mbit memory for flame delay, a high precision internal 10-bit A/D converter and D/A
converter, and adapting 10-bit signal processing (only for luminance signal) and high picture quality. The µPD64084 is
completely single-chip system of 3D Y/C separation.
This LSI includes the Wide Clear Vision ID signal (Japanese local format) decoder and ID-1 signal decoder.
FEATURES
On-chip 4-Mbit frame delay memory.
2 operation mode
Motion adaptive 3D Y/C separation
2D Y/C separation + Frame recursive Y/C NR
Embedded 10-bit A/D converter (1ch), 10-bit D/A converters (2ch), and System clock generator.
Embedded Y coring, Vertical enhancer, Peaking filter, and Noise detector.
Embedded ID-1 signal decoder, and WCV-ID signal decoder.
I2C bus control.
Dual power supply of 2.5 V and 3.3 V.
For digital : DVDD = 2.5 V
For analog : AVDD = 2.5 V
For DRAM : DVDDRAM = 2.5 V
For I/O : DVDDIO = 3.3 V
ORDERING INFORMATION
Part number
µPD64084GC-8EA-ANote1
µPD64084GC-8EA-YNote2
Package
100-pin plastic LQFP (fine pitch) (14 × 14 mm)
100-pin plastic LQFP (fine pitch) (14 × 14 mm)
Notes 1. Lead-free product
2. High-thermal-resistance product
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16021EJ2V0DS00 (2nd edition)
Date Published March 2003 NS CP (K)
Printed in Japan
The mark shows major revised points.
2002
Free Datasheet http://www.0PDF.com




D64084 pdf, 반도체, 판매, 대치품
µ PD64084
BLOCK DIAGRAM
10-bit Digital
Comp. Input
4-Mbit Frame
Memory
Comp. Input
BPF
Clamp
10-bit
ADC
8fSC PLL
8-bit
fSC DAC
4fSC
8fSC
20 MHz
Ext. Sync.
Separate
fSC/227.5fH
Dec.
Sync.
Separate
Timing
Generator
C Delay &
C Noise Reducer
Y/C Separator &
Y Noise Reducer
3-Line Comb Filter
Motion Detector
3-Line Comb Filter
3-Line Comb Filter
WCV-ID Dec.
ID-1 Dec.
Non-Std.
Detector
C
Y-Coring
Y-Peaking
Y
Y-Enhancer
ID-1 Enc.
10-bit
C-DAC
10-bit
Y-DAC
4fSC
Power
Down cont.
I2C Bus
I/F
C Output
Y Output
Digital YC
Output
I2C Bus
Line
4
Data Sheet S16021EJ2V0DS
Free Datasheet http://www.0PDF.com

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D64084 전자부품, 판매, 대치품
µ PD64084
8. NONSTANDARD SIGNAL DETECTION BLOCK ................................................................................................. 22
8.1 Horizontal Sync Nonstandard Signal Detection............................................................................................ 22
8.2 Vertical Sync Nonstandard Signal Detection ................................................................................................ 22
8.3 Frame Sync Nonstandard Signal Detection.................................................................................................. 22
8.4 Forced Standard or Nonstandard Signal Control.......................................................................................... 22
8.5 Noise Level Detection................................................................................................................................... 22
9. WCV-ID DECODER / ID-1 DECODER BLOCK..................................................................................................... 23
9.1 WCV-ID Decoder .......................................................................................................................................... 23
9.2 ID-1 Decoder ................................................................................................................................................ 24
10. Y SIGNAL OUTPUT PROCESSING BLOCK........................................................................................................ 25
10.1 Y High-Frequency Coring Circuit ................................................................................................................. 25
10.2 Y Peaking Filter Circuit ................................................................................................................................ 26
10.3 Vertical Aperture Compensation Circuit ...................................................................................................... 26
10.4 Turning On/Off Y Peaking and Vertical Aperture Compensation ................................................................. 26
10.5 ID-1 Encoder ............................................................................................................................................... 26
11. C SIGNAL OUTPUT PROCESSING BLOCK........................................................................................................ 27
11.1 C Signal Delay Adjustment .......................................................................................................................... 27
11.2 BPF and Gain Processing ........................................................................................................................... 27
12. VIDEO SIGNAL OUTPUT BLOCK........................................................................................................................ 28
12.1 Digital YC Output Processing ...................................................................................................................... 28
12.2 Video Signal Output Level ........................................................................................................................... 28
12.3 Pin Treatment .............................................................................................................................................. 29
13. EXTEND DIGITAL INPUT / OUTPUT.................................................................................................................... 30
13.1 Usage of extend digital I/O terminals........................................................................................................... 30
13.2 Digital YC output format .............................................................................................................................. 30
13.3 Pin Treatment .............................................................................................................................................. 30
14. DIGITAL CONNECTION WITH GHOST REDUCER IC µ PD64031A................................................................... 31
14.1 Outline ......................................................................................................................................................... 31
14.2 System Configuration and Control Method.................................................................................................. 33
14.2.1 Selecting video signal input path...................................................................................................... 33
14.2.2 Selecting mode according to clock and video signal input path ....................................................... 33
14.3 Setting of Digital Direct-Connected System ................................................................................................ 34
14.3.1 Hardware setting .............................................................................................................................. 34
14.3.2 Register setting ................................................................................................................................ 35
15. I2C BUS INTERFACE............................................................................................................................................. 36
15.1 Basic Specification ...................................................................................................................................... 36
15.2 Data Transfer Formats ................................................................................................................................. 37
15.3 Initialization.................................................................................................................................................. 38
15.4 Serial Bus Registers .................................................................................................................................... 39
15.5 Serial Bus Register Functions ..................................................................................................................... 41
Data Sheet S16021EJ2V0DS
7
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