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NT5CC256M16CP 데이터시트 PDF




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부품번호 NT5CC256M16CP 기능
기능 Industrial and Automotive DDR3(L) 4Gb SDRAM
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NT5CC256M16CP 데이터시트, 핀배열, 회로
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Nanya Technology Corp.
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Commercial, Industrial and Automotive DDR3(L) 4Gb SDRAM
Features
JEDEC DDR3 Compliant
- 8n Prefetch Architecture
- Differential Clock(CK/) and Data Strobe(DQS/)
- Double-data rate on DQs, DQS and DM
Data Integrity
- Auto Self Refresh (ASR) by DRAM built-in TS
- Auto Refresh and Self Refresh Modes
Power Saving Mode
- Partial Array Self Refresh (PASR)1
- Power Down Mode
Signal Integrity
- Configurable DS for system compatibility
- Configurable On-Die Termination
- ZQ Calibration for DS/ODT impedance accuracy via
external ZQ pad (240 ohm ± 1%)
Signal Synchronization
- Write Leveling via MR settings
- Read Leveling via MPR
Interface and Power Supply
- SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V)
- SSTL_1354 for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V)
Speed Grade (CL-TRCD-TRP) 2,3
- 2133 Mbps / 14-14-14
- 1866 Mbps / 13-13-13
- 1600 Mbps / 11-11-11
Options
Temperature Range (Tc) 5
- Commercial Grade = 0~95
- Industrial Grade = -40~95
- Automotive Grade 2 = -40~105
- Automotive Grade 3 = -40~95
Programmable Functions
CAS Latency (5/6/7/8/9/10/11/12/13/14)
CAS Write Latency (5/6/7/8/9/10)
Additive Latency (0/CL-1/CL-2)
Write Recovery Time (5/6/7/8/10/12/14/16)
Burst Type (Sequential/Interleaved)
Burst Length (BL8/BC4/BC4 or 8 on the fly)
Self RefreshTemperature Range(Normal/Extended)
Output Driver Impedance (34/40)
On-Die Termination of Rtt_Nom(20/30/40/60/120)
On-Die Termination of Rtt_WR(60/120)
Precharge Power Down (slow/fast)
Packages / Density Information
Lead-free RoHS compliance and Halogen-free
Density and Addressing
4Gb
(Org. / Package)
Length x Width
(mm)
Ball pitch
(mm)
512Mbx8
78-ball
TFBGA
9.00 x 10.50
0.80
256Mbx16
96-ball
TFBGA
9.00 x 13.00
0.80
Organization
Bank Address
Auto precharge
BL switch on the fly
Row Address
Column Address
Page Size
tRFC(ns) 6
512Mb x 8
BA0 BA2
A10 / AP
A12 / 
A0 A15
A0 A9
1KB
260ns
256Mb x 16
BA0 BA2
A10 / AP
A12 / 
A0 A14
A0 A9
2KB
260ns
Notes:
1. Default state of PASR is disabed. This is enabled by using an electrical fuse. Please contact with NTC for the demand.
2. The timing specification of high speed bin is backward compatible with low speed bin.
3. Please refer to ordering information for the deailts (DDR3, DDR3L, DDR3L RS).
4. SSTL_135 compatible to SSTL_15.
5. If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9us interval refresh rate. Extended SRT or ASR must be enabled.
6. Violating tRFC specification will induce malfunction.
1
Version 1.3
08/ 2013
Nanya Technology Cooperation ©
All Rights Reserved.
Free Datasheet http://www.0PDF.com




NT5CC256M16CP pdf, 반도체, 판매, 대치품
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Ordering Information
Organization
Part Number
Package
Speed3
Clock (MHz) Data Rate (Mb/s) CL-TRCD-TRP
DDR3 Commercial Grade
NT5CB512M8CN-DI
800 DDR3-1600 11-11-11
512M x 8 NT5CB512M8CN-EK
78-Ball TFBGA
933
DDR3-1866
13-13-13
NT5CB512M8CN-FL
1066
DDR3-2133
14-14-14
NT5CB256M16CP-DI
800 DDR3-1600 11-11-11
256M x 16 NT5CB256M16CP-EK 96-Ball TFBGA
933
DDR3-1866
13-13-13
NT5CB256M16CP-FL
1066
DDR3-2133
14-14-14
Organization
512M x 8
Part Number
DDR3L Commercial Grade
Package
Speed3
Clock (MHz) Data Rate (Mb/s) CL-TRCD-TRP
NT5CC512M8CN-DI
NT5CC512M8CN-DIB1
78-Ball TFBGA
800
800
DDR3L-1600
DDR3L RS-1600
11-11-11
11-11-11
256M x 16
NT5CC256M16CP-DI
NT5CC256M16CP-DIB1
96-Ball TFBGA
800
800
DDR3L-1600
DDR3L RS-1600
11-11-11
11-11-11
Industrial Grade
512M x 8
NT5CB512M8CN-DII
NT5CC512M8CN-DII
78-Ball TFBGA
800
800
DDR3-1600
DDR3L-1600
11-11-11
11-11-11
256M x 16
256M x 16
256M x 16
NT5CB256M16CP-DII
NT5CC256M16CP-DII
96-Ball TFBGA
800
800
Automotive Grade 2 2
NT5CB256M16CP-DIH 96-Ball TFBGA
800
Automotive Grade 3 2
NT5CB256M16CP-DIA 96-Ball TFBGA
800
DDR3-1600
DDR3L-1600
11-11-11
11-11-11
DDR3-1600
11-11-11
DDR3-1600
11-11-11
Notes:
1. Reduced Standby
2. Please confirm with NTC for the available schedule.
3. The timing specification of high speed bin is backward compatible with low speed bin.
Version 1.3
08/ 2013
4
Nanya Technology Cooperation ©
All Rights Reserved.
Free Datasheet http://www.0PDF.com

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NT5CC256M16CP 전자부품, 판매, 대치품
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Ball Configuration 96 Ball BGA Package (X16)
<TOP View>
See the balls through the package
1
A VDDQ
B VSSQ
C VDDQ
D VSSQ
E VSS
F VDDQ
G VSSQ
H VREFDQ
J NC
K ODT
L NC
M VSS
N VDD
P VSS
R VDD
T VSS
1
2
DQU5
VDD
DQU3
VDDQ
VSSQ
DQL2
DQL6
VDDQ
VSS
VDD

BA0
A3
A5
A7
REET
2
3
DQU7
VSS
DQU1
DMU
DQL0
DQSL
L
DQL4
RA
A
WE
BA2
A0
A2
A9
A13
3
456
456
7
DQU4
U
DQSU
DQU0
DML
DQL1
VDD
DQL7
CK

A10/AP
NC
A12/
A1
A11
A14
7
8
VDDQ
DQU6
DQU2
VSSQ
VSSQ
DQL3
VSS
DQL5
VSS
VDD
ZQ
VREFCA
BA1
A4
A6
A8
8
9
VSS
VSSQ
VDDQ
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
CKE
NC
VSS
VDD
VSS
VDD
VSS
9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Unit: mm
* BSC (Basic Spacing between Center)
Version 1.3
08/ 2013
7
Nanya Technology Cooperation ©
All Rights Reserved.
Free Datasheet http://www.0PDF.com

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NT5CC256M16CP

Industrial and Automotive DDR3(L) 4Gb SDRAM

Nanya
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