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PDF NT5CC1024M4CN Data sheet ( Hoja de datos )
| Número de pieza | NT5CC1024M4CN | |
| Descripción | 4Gb DDR3 SDRAM C-Die | |
| Fabricantes | Nanya | |
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4Gb DDR3 SDRAM C-Die
NT5CB1024M4CN / NT5CB512M8CN / NT5CB256M16CP
NT5CC1024M4CN / NT5CC512M8CN / NT5CC256M16CP
Feature
VDD = VDDQ = 1.5V ± 0.075V (JEDEC Standard
Power Supply)
VDD = VDDQ = 1.35V -0.0675V/+0.1V
(Backward Compatible to VDD = VDDQ = 1.5V
±0.075V)
8 Internal memory banks (BA0- BA2)
Differential clock input (CK, )
Programmable Latency: 5, 6, 7, 8, 9, 10, 11, 12,
13
WRITE Latency (CWL): 5,6,7,8,9, 10
POSTED CAS ADDITIVE Programmable Additive
Latency (AL): 0, CL-1, CL-2 clock
Programmable Sequential / Interleave Burst Type
Programmable Burst Length: 4, 8
Through ZQ pin (RZQ:240 ohm±1%)
8n-bit prefetch architecture
Output Driver Impedance Control
Differential bidirectional data strobe
Internal(self) calibration:Internal self calibration
OCD Calibration
Dynamic ODT (Rtt_Nom & Rtt_WR)
Auto Self-Refresh
Self-Refresh Temperature
RoHS compliance and Halogen free
Packages:
78-Balls BGA for x4/x8 components
96-Ball BGA for x16 components
Description
The 4Gb Double-Data-Rate-3 (DDR3) DRAMs is a high-speed CMOS Double Data Rate32 SDRAM containing
4,294,967,296 bits. It is internally configured as an octal-bank DRAM.
The 4Gb chip is organized as 128Mbit x 4 I/O x 8 bank , 64Mbit x 8 I/O x 8 banks and 32Mbit x16 I/O x 8 banks. These
synchronous devices achieve high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are
synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks
(CK rising and falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source
synchronous fashion.
These devices operate with a single 1.5V ± 0.075V and 1.35V -0.0675V/+0.1V power supply and are available in BGA
packages.
REV 1.0
04/ 2012
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1 page  
4Gb DDR3 SDRAM C-Die
NT5CB1024M4CN / NT5CB512M8CN / NT5CB256M16CP
NT5CC1024M4CN / NT5CC512M8CN / NT5CC256M16CP
Symbol
CK,
CKE
, ,
DM
(DMU, DML)
BA[2:0]
A10 / AP
A[15:0]
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input / Output Functional Description
Function
Clock: CK and are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of .
Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals
and device input buffers and output drivers. Taking CKE low provides Precharge
Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row
Active in any bank). CKE is synchronous for power down entry and exit and for
Self-Refresh entry. CKE is asynchronous for Self-Refresh exit. After VREF has
become stable during the power on and initialization sequence, it must be maintained
for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF
must maintain to this input. CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK, , ODT and CKE are disabled during Power
Down. Input buffers, excluding CKE, are disabled during Self-Refresh.
Chip Select: All commands are masked when is registered high. provides for
external rank selection on systems with multiple memory ranks. is considered part
of the command code.
Command Inputs: , and (along with ) define the command being
entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH coincident with that input data during a Write access. DM is
sampled on both edges of DQS. For x8 device, the function of DM or TDQS / is
enabled by Mode Register A11 setting in MR1
Bank Address Inputs: BA0, BA1, and BA2 define to which bank an Active, Read,
Write or Precharge command is being applied. Bank address also determines which
mode register is to be accessed during a MRS cycle.
Auto-Precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/Write
operation. (HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a
Precharge command to determine whether the Precharge applies to one bank (A10
LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is
selected by bank addresses.
Address Inputs: Provide the row address for Activate commands and the column
address for Read/Write commands to select one location out of the memory array in
the respective bank. (A10/AP and A12/ have additional function as below.) The
address inputs also provide the op-code during Mode Register Set commands.
REV1.0
04/ 2012
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4Gb DDR3 SDRAM C-Die
NT5CB1024M4CN / NT5CB512M8CN / NT5CB256M16CP
NT5CC1024M4CN / NT5CC512M8CN / NT5CC256M16CP
“High” after Reset, CKE needs to be continuously registered “High” until the initialization sequence is finished,
including expiration of tDLLK and tZQinit.
4. The DDR3(L) DRAM will keep its on-die termination in high impedance state as long as is asserted. Further,
the DRAM keeps its on-die termination in high impedance state after de-assertion until CKE is registered HIGH.
The ODT input signal may be in undefined state until tIS before CKE is registered HIGH. When CKE is registered
HIGH, the ODT input signal may be statically held at either LOW or HIGH. If RTT_NOM is to be enabled in MR1, the
ODT input signal must be statically held LOW. In all cases, the ODT input signal remains static until the power up
initialization sequence is finished, including the expiration of tDLLK and tZQinit.
5. After CKE being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS command
to load mode register. [tXPR=max (tXS, 5tCK)]
6. Issue MRS command to load MR2 with all application settings. (To issue MRS command for MR2, provide “Low” to
BA0 and BA2, “High” to BA1)
7. Issue MRS command to load MR3 with all application settings. (To issue MRS command for MR3, provide “Low” to
BA2, “High” to BA0 and BA1)
8. Issue MRS command to load MR1 with all application settings and DLL enabled. (To issue “DLL Enable” command,
provide “Low” to A0, “High” to BA0 and “Low” to BA1 and BA2)
9. Issue MRS Command to load MR0 with all application settings and “DLL reset”. (To issue DLL reset command,
provide “High” to A8 and “Low” to BA0-BA2)
10. Issue ZQCL command to starting ZQ calibration.
11. Wait for both tDLLK and tZQinit completed.
12. The DDR3(L) SDRAM is now ready for normal operation.
REV1.0
04/ 2012
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