|
|
PDF AT25DF161 Data sheet ( Hoja de datos )
| Número de pieza | AT25DF161 | |
| Descripción | 16-Megabit 2.3V or 2.7V Minimum SPI Serial Flash Memory | |
| Fabricantes | Adesto | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AT25DF161 (archivo pdf) en la parte inferior de esta página. Total 52 Páginas | ||
|
No Preview Available !
Features
• Single 2.3V - 3.6V or 2.7V - 3.6V Supply
• Serial Peripheral Interface (SPI) Compatible
– Supports SPI Modes 0 and 3
– Supports RapidS Operation
– Supports Dual-Input Program and Dual-Output Read
• Very High Operating Frequencies
– 100MHz for RapidS
– 85MHz for SPI
– Clock-to-Output (tV) of 5ns Maximum
• Flexible, Optimized Erase Architecture for Code + Data Storage Applications
– Uniform 4-Kbyte Block Erase
– Uniform 32-Kbyte Block Erase
– Uniform 64-Kbyte Block Erase
– Full Chip Erase
• Individual Sector Protection with Global Protect/Unprotect Feature
– 32 Sectors of 64-Kbytes Each
• Hardware Controlled Locking of Protected Sectors via WP Pin
• Sector Lockdown
– Make Any Combination of 64-Kbyte Sectors Permanently Read-Only
• 128-Byte Programmable OTP Security Register
• Flexible Programming
– Byte/Page Program (1- to 256-Bytes)
• Fast Program and Erase Times
– 1.0ms Typical Page Program (256-Bytes) Time
– 50ms Typical 4-Kbyte Block Erase Time
– 250ms Typical 32-Kbyte Block Erase Time
– 400ms Typical 64-Kbyte Block Erase Time
• Program and Erase Suspend/Resume
• Automatic Checking and Reporting of Erase/Program Failures
• Software Controlled Reset
• JEDEC Standard Manufacturer and Device ID Read Methodology
• Low Power Dissipation
– 5mA Active Read Current (Typical at 20MHz)
– 5µA Deep Power-Down Current (Typical)
• Endurance: 100,000 Program/Erase Cycles
• Data Retention: 20 Years
• Complies with Full Industrial Temperature Range
• Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (150-mil and 208-mil wide)
– 8-pad Ultra Thin DFN (5 x 6 x 0.6mm)
16-Megabit
2.3V or 2.7V
Minimum
SPI Serial Flash
Memory
AT25DF161
(Not Recommended
for New Designs)
3687H–DFLASH–5/2013
1 page  
Figure 4-1.
Memory Architecture Diagram
AT25DF161
3687H–DFLASH–5/2013
5
Free Dat
5 Page 
AT25DF161
the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be
reset back to the logical “0” state if the program cycle aborts due to an incomplete address being sent, an incomplete
byte of data being sent, the CS pin being deasserted on uneven byte boundaries, or because the memory location to be
programmed is protected or locked down.
While the device is programming, the Status Register can be read and will indicate that the device is busy. For faster
throughput, it is recommended that the Status Register be polled rather than waiting the tBP or tPP time to determine if the
data bytes have finished programming. At some point before the program cycle completes, the WEL bit in the Status
Register will be reset back to the logical “0” state.
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program
properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.
Figure 8-1. Byte Program
CS
SCK
SI
SO
23&2'(
$''5(66%,76$$
'$7$,1
$$$$$$
06%
06%
$$$''''''''
06%
+,*+,03('$1&(
Figure 8-2. Page Program
CS
SCK
SI
SO
23&2'(
$''5(66%,76$$
'$7$,1%<7(
$$$
06%
06%
$$$''''''''
06%
+,*+,03('$1&(
'$7$,1%<7(Q
''''''''
06%
8.2 Dual-Input Byte/Page Program
The Dual-Input Byte/Page Program command is similar to the standard Byte/Page Program command and can be used to
program anywhere from a single byte of data up to 256-bytes of data into previously erased memory locations. Unlike the
standard Byte/Page Program command, however, the Dual-Input Byte/Page Program command allows two bits of data to
be clocked into the device on every clock cycle rather than just one.
Before the Dual-Input Byte/Page Program command can be started, the Write Enable command must have been
previously issued to the device (see “Write Enable” on page 18) to set the Write Enable Latch (WEL) bit of the Status
Register to a logical “1” state. To perform a Dual-Input Byte/Page Program command, an opcode of A2h must be clocked
3687H–DFLASH–5/2013
11
Free Dat
11 Page | ||
| Páginas | Total 52 Páginas | |
| PDF Descargar | [ Datasheet AT25DF161.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AT25DF161 | 16-Megabit 2.3V or 2.7V Minimum SPI Serial Flash Memory | Adesto |
| AT25DF161 | 16-Megabit 2.7-volt Minimum SPI Serial Flash Memory |  ATMEL Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |