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PDF L6743D Data sheet ( Hoja de datos )
| Número de pieza | L6743D | |
| Descripción | High current MOSFET driver | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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L6743D
High current MOSFET driver
Features
■ Dual MOSFET driver for synchronous rectified
converters
■ High driving current for fast external MOSFET
switching
■ Integrated bootstrap diode
■ High frequency operation
■ Enable pin
■ Adaptive dead-time management
■ Flexible gate-drive: 5 V to 12 V compatible
■ High-impedance (HiZ) management for output
stage shutdown
■ Preliminary OV protection
■ SO8 package
Applications
■ High current VRM / VRD for desktop / server /
workstation CPUs
■ High current and high efficiency DC / DC
converter
Description
L6743D is a flexible, high-frequency dual-driver
specifically designed to drive N-channel
MOSFETs connected in synchronous-rectified
buck topology.
SO8
Combined with ST PWM controllers, the driver
allows implementing complete voltage regulator
solutions for modern high-current CPUs and
DCDC conversion in general. L6743D embeds
high-current drivers for both high-side and low-
side MOSFETS. The device accepts flexible
power supply (5 V to 12 V) to optimize the gate-
drive voltage for high-side and low-side
maximizing the system efficiency.
The bootstrap diode is embedded saving the use
of external diodes. Anti shoot-through
management avoids high-side and low-side
MOSFET to conduct simultaneously and,
combined with adaptive dead-time control,
minimizes the LS body diode conduction time.
L6743D embeds preliminary OV protection: after
Vcc overcomes the UVLO and while the device is
in HiZ, the LS MOSFET is turned ON to protect
the load in case the output voltage overcomes a
warning threshold protecting the output against
HS failures.
The driver is available is SO8 package.
Table 1.
Device summary
Order codes
L6743D
L6743DTR
Package
SO8
Packing
Tube
Tape and reel
December 2008
Rev 1
1/16
www.st.com
1
Free Datasheet http://www.Datasheet4U.com
1 page  
L6743D
Pins description and connection diagrams
2.2
Thermal data
Table 3. Thermal data
Symbol
Parameter
RTHJA
TMAX
TSTG
TJ
PTOT
Thermal resistance junction to ambient
(Device soldered on 2s2p, 67 mm x 69 mm board)
Maximum junction temperature
Storage temperature range
Junction temperature range
Maximum power dissipation at 25 °C
(Device soldered on 2s2p PC board)
Value
Unit
85 °C/W
150
0 to 150
0 to 125
°C
°C
°C
1.15 W
5/16
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5 Page 
L6743D
Device description and operation
Referring to Figure 6, classical MOSFET driver can be represented by a push-pull output
stage with two different MOSFETs: P-MOSFET to drive the external gate high and N-
MOSFET to drive the external gate low (with their own RdsON: Rhi_HS, Rlo_HS, Rhi_LS,
Rlo_LS). The external power MOSFET can be represented in this case as a capacitance
(CG_HS, CG_LS) that stores the gate-charge (QG_HS, QG_LS) required by the external power
MOSFET to reach the driving voltage (PVCC for HS and VCC for LS). This capacitance is
charged and discharged at the driver switching frequency FSW.
The total power Psw is dissipated among the resistive components distributed along the
driving path. According to the external Gate resistance and the power-MOSFET intrinsic
gate resistance, the driver dissipates only a portion of Psw as follow:
PSW – HS
=
1--
2
⋅
CGHS
⋅
PVCC2
⋅
Fsw
⋅
⎛
⎝
-------------------------R----h---i--H---S--------------------------
RhiHS + RGateHS + RiHS
+
-R----l-o---H----S-----+-----R--R--G--l--oa---Ht--e-S--H---S-----+-----R-----i-H----S-⎠⎞
PSW – LS
=
1--
2
⋅
CGLS
⋅
VCC2
⋅
Fsw
⋅
⎛
⎝
------------------------R-----h---i-L---S-------------------------
RhiLS + RGateLS + RiLS
+
-R----l-o---L---S-----+-----R--R--G---l-oa---Lt--e-S--L---S-----+----R-----i-L---S--⎠⎞
The total power dissipated from the driver can then be determined as follow:
P = PDC + PSW – HS + PSW – LS
Figure 6. Equivalent circuit for MOSFET drive
VCC
VCC
BOOT
RGATELS RILS
LGATE
CGLS
GND
LS DRIVER
LS MOSFET
RGATEHS RIHS
HGATE
CGHS
PHASE
HS DRIVER
HS MOSFET
4.5 Layout guidelines
L6743D provides driving capability to implement high-current step-down DC-DC converters.
The first priority when placing components for these applications has to be reserved to the
power section, minimizing the length of each connection and loop as much as possible. To
minimize noise and voltage spikes (also EMI and losses) power connections must be a part
of a power plane and anyway realized by wide and thick copper traces: loop must be anyway
minimized. The critical components, such as the power MOSFETs, must be close one to the
other. However, some space between the power MOSFET is still required to assure good
thermal cooling and airflow.
Traces between the driver and the MOSFETS should be short and wide to minimize the
inductance of the trace so minimizing ringing in the driving signals. Moreover, VIAs count
needs to be minimized to reduce the related parasitic effect.
11/16
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11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet L6743D.PDF ] | |
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