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48LC4M32B2 데이터시트 PDF




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48LC4M32B2 데이터시트, 핀배열, 회로
SDR SDRAM
MT48LC4M32B2 – 1 Meg x 32 x 4 Banks
128Mb: x32 SDRAM
Features
Features
• PC100-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge
and auto refresh modes
• Self refresh mode (not available on AT devices)
• Auto refresh
– 64ms, 4096-cycle refresh (commercial and
industrial)
– 16ms, 4096-cycle refresh (automotive)
• LVTTL-compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• Supports CAS latency (CL) of 1, 2, and 3
Options
• Configuration
– 4 Meg x 32 (1 Meg x 32 x 4 banks)
• Package – OCPL1
– 86-pin TSOP II (400 mil)
– 86-pin TSOP II (400 mil) Pb-free
– 90-ball VFBGA (8mm x 13mm)
– 90-ball VFBGA (8mm x 13mm) Pb-
free
• Timing (cycle time)
– 6ns (166 MHz)
– 6ns (166 MHz)
– 7ns (143 MHz)
• Revision
• Operating temperature range
– Commercial (0°C to +70°C)
– Industrial (–40°C to +85°C)
– Automotive (–40°C to +105°C)
Marking
4M32B2
TG
P
F5
B5
-6A2
-63
-73
:G/:L
None
IT
AT4
Notes:
1. Off-center parting line.
2. Available only on Revision L.
3. Available only on Revision G.
4. Contact Micron for availability.
Table 1: Key Timing Parameters
CL = CAS (READ) latency
Clock
Speed Grade
Frequency (MHz)
-6A 167
-6 167
-7 143
Target tRCD-tRP-CL
3-3-3
3-3-3
3-3-3
tRCD (ns)
18
18
20
tRP (ns)
18
18
20
CL (ns)
18
18
21
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2001 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Free Datasheet http://www.Datasheet4U.com




48LC4M32B2 pdf, 반도체, 판매, 대치품
128Mb: x32 SDRAM
Features
List of Figures
Figure 1: 4 Meg x 32 Functional Block Diagram ................................................................................................. 8
Figure 2: 86-Pin TSOP Pin Assignments (Top View) ........................................................................................... 9
Figure 3: 90-Ball FBGA Ball Assignments (Top View) ....................................................................................... 10
Figure 4: 86-Pin Plastic TSOP II (400 mil) – Package Codes TG/P ...................................................................... 12
Figure 5: 90-Ball VFBGA (8mm x 13mm) ......................................................................................................... 13
Figure 6: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ................................................. 15
Figure 7: Example: Temperature Test Point Location, 90-Ball VFBGA (Top View) .............................................. 16
Figure 8: ACTIVE Command .......................................................................................................................... 25
Figure 9: READ Command ............................................................................................................................. 26
Figure 10: WRITE Command ......................................................................................................................... 27
Figure 11: PRECHARGE Command ................................................................................................................ 28
Figure 12: Initialize and Load Mode Register .................................................................................................. 36
Figure 13: Mode Register Definition ............................................................................................................... 38
Figure 14: CAS Latency .................................................................................................................................. 41
Figure 15: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3 .......................................................... 42
Figure 16: Consecutive READ Bursts .............................................................................................................. 44
Figure 17: Random READ Accesses ................................................................................................................ 45
Figure 18: READ-to-WRITE ............................................................................................................................ 46
Figure 19: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 47
Figure 20: READ-to-PRECHARGE .................................................................................................................. 47
Figure 21: Terminating a READ Burst ............................................................................................................. 48
Figure 22: Alternating Bank Read Accesses ..................................................................................................... 49
Figure 23: READ Continuous Page Burst ......................................................................................................... 50
Figure 24: READ – DQM Operation ................................................................................................................ 51
Figure 25: WRITE Burst ................................................................................................................................. 52
Figure 26: WRITE-to-WRITE .......................................................................................................................... 53
Figure 27: Random WRITE Cycles .................................................................................................................. 54
Figure 28: WRITE-to-READ ............................................................................................................................ 54
Figure 29: WRITE-to-PRECHARGE ................................................................................................................. 55
Figure 30: Terminating a WRITE Burst ............................................................................................................ 56
Figure 31: Alternating Bank Write Accesses ..................................................................................................... 57
Figure 32: WRITE – Continuous Page Burst ..................................................................................................... 58
Figure 33: WRITE – DQM Operation ............................................................................................................... 59
Figure 34: READ With Auto Precharge Interrupted by a READ ......................................................................... 61
Figure 35: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 62
Figure 36: READ With Auto Precharge ............................................................................................................ 63
Figure 37: READ Without Auto Precharge ....................................................................................................... 64
Figure 38: Single READ With Auto Precharge .................................................................................................. 65
Figure 39: Single READ Without Auto Precharge ............................................................................................. 66
Figure 40: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 67
Figure 41: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 67
Figure 42: WRITE With Auto Precharge ........................................................................................................... 68
Figure 43: WRITE Without Auto Precharge ..................................................................................................... 69
Figure 44: Single WRITE With Auto Precharge ................................................................................................. 70
Figure 45: Single WRITE Without Auto Precharge ............................................................................................ 71
Figure 46: Auto Refresh Mode ........................................................................................................................ 73
Figure 47: Self Refresh Mode .......................................................................................................................... 75
Figure 48: Power-Down Mode ........................................................................................................................ 76
Figure 49: Clock Suspend During WRITE Burst ............................................................................................... 77
Figure 50: Clock Suspend During READ Burst ................................................................................................. 78
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
4 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2001 Micron Technology, Inc. All rights reserved.
Free Datasheet http://www.Datasheet4U.com

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48LC4M32B2 전자부품, 판매, 대치품
128Mb: x32 SDRAM
General Description
General Description
The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing
134,217,728 bits. It is internally configured as a quad-bank DRAM with asynchronous
interface (all signals are registered on the positive edge of the clock signal, CLK). Each of
the 33,554,432-bit banks is organized as 4096 rows by 256 columns by 32 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed se-
quence. Accesses begin with the registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the
bank; A[11:0] select the row).The address bits registered coincident with the READ or
WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8
locations, or the full page, with a burst terminate option. An auto precharge function
may be enabled to provide a self-timed row precharge that is initiated at the end of the
burst sequence.
The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-
tion. This architecture is compatible with the 2n rule of prefetch architectures, but it al-
so allows the column address to be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank while accessing one of the other
three banks will hide the precharge cycles and provide seamless, high-speed, random-
access operation.
The 64Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh
mode is provided, along with a power-saving, power-down mode. All inputs and out-
puts are LVTTL-compatible.
The devices offer substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks to hide precharge time, and
the capability to randomly change column addresses on each clock cycle during a burst
access.
Automotive Temperature
The automotive temperature (AT) option adheres to the following specifications:
• 16ms refresh rate
• Self refresh not supported
• Ambient and case temperature cannot be less than –40°C or greater than 105°C
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
7 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2001 Micron Technology, Inc. All rights reserved.
Free Datasheet http://www.Datasheet4U.com

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