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PDF AD5694 Data sheet ( Hoja de datos )
| Número de pieza | AD5694 | |
| Descripción | (AD5694 / AD5696) 16-/12-Bit nanoDAC+ | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
FEATURES
High relative accuracy (INL): ±2 LSB maximum at 16 bits
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
Total unadjusted error (TUE): ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User-selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
400 kHz I2C-compatible serial interface
4 I2C addresses available
Low glitch: 0.5 nV-sec
Robust 3.5 kV HBM and 1.5 kV FICDM ESD rating
Low power: 1.8 mW at 3 V
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
APPLICATIONS
Digital gain and offset adjustment
Programmable attenuators
Process control (PLC I/O cards)
Industrial automation
Data acquisition systems
GENERAL DESCRIPTION
The AD5696 and AD5694, members of the nanoDAC+™ family,
are low power, quad, 16-/12-bit buffered voltage output DACs.
The devices include a gain select pin giving a full-scale output
of 2.5 V (gain = 1) or 5 V (gain = 2). The devices operate from
a single 2.7 V to 5.5 V supply, are guaranteed monotonic by
design, and exhibit less than 0.1% FSR gain error and 1.5 mV
offset error performance. The devices are available in a 3 mm ×
3 mm LFCSP package and in a TSSOP package.
The AD5696/AD5694 incorporate a power-on reset circuit and a
RSTSEL pin; the RSTSEL pin ensures that the DAC outputs power
up to zero scale or midscale and remain at that level until a valid
write takes place. The parts contain a per-channel power-down
feature that reduces the current consumption of the device in
power-down mode to 4 µA at 3 V.
The AD5696/AD5694 use a versatile 2-wire serial interface that
operates at clock rates up to 400 kHz and include a VLOGIC pin
intended for 1.8 V/3 V/5 V logic.
Quad, 16-/12-Bit nanoDAC+
with I2C Interface
AD5696/AD5694
FUNCTIONAL BLOCK DIAGRAM
VDD
GND
VREF
VLOGIC
SCL
SDA
AD5696/AD5694
INPUT
REGISTER
INPUT
REGISTER
DAC
STRING
REGISTER DAC A
DAC
STRING
REGISTER DAC B
A1
INPUT
DAC
STRING
REGISTER REGISTER DAC C
A0
INPUT
DAC
STRING
REGISTER REGISTER DAC D
POWER-ON
RESET
GAIN =
×1/×2
LDAC RESET
RSTSEL
Figure 1.
GAIN
BUFFER
VOUTA
BUFFER
VOUTB
BUFFER
VOUTC
BUFFER
POWER-
DOWN
LOGIC
VOUTD
Table 1. Quad nanoDAC+ Devices
Interface Reference 16-Bit
SPI
Internal
AD5686R
External AD5686
I2C
Internal
AD5696R
External AD5696
14-Bit
AD5685R
AD5695R
12-Bit
AD5684R
AD5684
AD5694R
AD5694
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5696 (16-bit): ±2 LSB maximum
AD5694 (12-bit): ±1 LSB maximum
2. Excellent DC Performance.
Total unadjusted error: ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
3. Two Package Options.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Free Datasheet http://www.Datasheet4U.com
1 page  
Data Sheet
AD5696/AD5694
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; RL = 2 kΩ; CL = 200 pF; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2
Output Voltage Settling Time
AD5696
AD5694
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Multiplying Bandwidth
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Total Harmonic Distortion4
Output Noise Spectral Density
Output Noise
Signal-to-Noise Ratio (SNR)
Spurious-Free Dynamic Range (SFDR)
Signal-to-Noise-and-Distortion Ratio
(SINAD)
Min
Typ Max Unit
Test Conditions/Comments3
¼ to ¾ scale settling to ±2 LSB
58
µs
57
µs
0.8 V/µs
0.5
nV-sec
1 LSB change around major carry transition
0.13 nV-sec
500 kHz
0.1 nV-sec
0.2 nV-sec
0.3 nV-sec
−80 dB At TA, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
100
nV/√Hz
DAC code = midscale, 10 kHz, gain = 2
6
µV p-p
0.1 Hz to 10 Hz
90 dB At TA, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
83 dB At TA, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
80 dB At TA, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
1 Guaranteed by design and characterization; not production tested.
2 See the Terminology section.
3 Temperature range is −40°C to +105°C; typical at 25°C.
4 Digitally generated sine wave at 1 kHz.
Rev. A | Page 5 of 24
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5 Page 
Data Sheet
0.10
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
2.7 3.2 3.7 4.2 4.7 5.2
SUPPLY VOLTAGE (V)
Figure 17. TUE vs. Supply Voltage, Gain = 1
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.07
–0.08
–0.09
–0.10
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
0 10000 20000
30000 40000
CODE
50000
Figure 18. TUE vs. Code, AD5696
60000 65535
VDD = 5V
25 TA = 25°C
REFERENCE = 2.5V
20
15
10
5
0
540
560 580 600 620
IDD (mA)
Figure 19. IDD Histogram at 5 V
640
AD5696/AD5694
1.0
0.8
0.6
0.4
SINKING, 2.7V
0.2 SINKING, 5V
0
–0.2
–0.4
SOURCING, 5V
–0.6
–0.8
SOURCING, 2.7V
–1.0
0
5 10 15 20 25
LOAD CURRENT (mA)
Figure 20. Headroom/Footroom vs. Load Current
30
7
VDD = 5V
6 TA = 25°C
REFERENCE = 2.5V
GAIN = 2
5
0xFFFF
4 0xC000
3
0x8000
2
0x4000
1
0x0000
0
–1
–2
–0.06
–0.04
–0.02
0
0.02
LOAD CURRENT (A)
0.04
Figure 21. Source and Sink Capability at 5 V
0.06
5
VDD = 3V
TA = 25°C
4 REFERENCE = 2.5V
GAIN = 1
3
2
1
0
–1
0xFFFF
0xC000
0x8000
0x4000
0x0000
–2
–0.06
–0.04 –0.02
0
0.02 0.04
LOAD CURRENT (A)
Figure 22. Source and Sink Capability at 3 V
0.06
Rev. A | Page 11 of 24
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11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD5694.PDF ] | |
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