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ATXMEGA256A3U PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 ATXMEGA256A3U
기능 8/16-bit Atmel XMEGA A3U Microcontroller
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ATXMEGA256A3U 데이터시트, 핀배열, 회로
8/16-bit Atmel XMEGA A3U Microcontroller
ATxmega256A3U / ATxmega192A3U /
ATxmega128A3U / ATxmega64A3U
Features
High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller
Nonvolatile program and data memories
64K - 256KBytes of in-system self-programmable flash
4K - 8KBytes boot section
2K - 4KBytes EEPROM
4K - 16KBytes internal SRAM
Peripheral features
Four-channel DMA controller
Eight-channel event system
Seven 16-bit timer/counters
Four timer/counters with four output compare or input capture channels
Three timer/counters with two output compare or input capture
channels
High resolution extension on all timer/counters
Advanced waveform extension (AWeX) on one timer/counter
One USB device interface
USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device
compliant
32 Endpoints with full configuration flexibility
Seven USARTs with IrDA support for one USART
Two two-wire interfaces with dual address match (I2C and SMBus compatible)
Three serial peripheral interfaces (SPIs)
AES and DES crypto engine
CRC-16 (CRC-CCITT) and CRC-32 (IEEE® 802.3) generator
16-bit real time counter (RTC) with separate oscillator
Two sixteen-channel, 12-bit, 2msps Analog to Digital Converters
One two-channel, 12-bit, 1msps Digital to Analog Converter
Four Analog Comparators with window compare function, and current sources
External interrupts on all general purpose I/O pins
Programmable watchdog timer with separate on-chip ultra low power oscillator
QTouch® library support
Capacitive touch buttons, sliders and wheels
Special microcontroller features
Power-on reset and programmable brown-out detection
Internal and external clock options with PLL and prescaler
Programmable multilevel interrupt controller
Five sleep modes
Programming and debug interfaces
JTAG (IEEE 1149.1 compliant) interface, including boundary scan
PDI (program and debug interface)
I/O and packages
50 Programmable I/O pins
64-lead TQFP
64-pad QFN
Operating voltage
1.6 – 3.6V
Operating frequency
0 – 12MHz from 1.6V
0 – 32MHz from 2.7V
Atmel-8386D-AVR-ATxmega64A3U-128A3U-192A3U-256A3U–03/2014
Free Datasheet http://www.Datasheet4U.com




ATXMEGA256A3U pdf, 반도체, 판매, 대치품
3. Overview
The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based
on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA device
achieves throughputs CPU approaching one million instructions per second (MIPS) per megahertz, allowing the system
designer to optimize power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly
connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction,
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times
faster than conventional single-accumulator or CISC based microcontrollers.
The AVR XMEGA A3U devices provide the following features: in-system programmable flash with read-while-write
capabilities; internal EEPROM and SRAM; four-channel DMA controller, eight-channel event system and programmable
multilevel interrupt controller, 50 general purpose I/O lines, 16-bit real-time counter (RTC); seven flexible, 16-bit
timer/counters with compare and PWM channels; seven USARTs; two two-wire serial interfaces (TWIs); one full speed
USB 2.0 interface; three serial peripheral interfaces (SPIs); AES and DES cryptographic engine; two 16-channel, 12-bit
ADCs with programmable gain; one 2-channel 12-bit DAC; four analog comparators (ACs) with window mode;
programmable watchdog timer with separate internal oscillator; accurate internal oscillators with PLL and prescaler; and
programmable brown-out detection.
The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available. The
devices also have an IEEE std. 1149.1 compliant JTAG interface, and this can also be used for boundary scan, on-chip
debug and programming.
The ATx devices have five software selectable power saving modes. The idle mode stops the CPU while allowing the
SRAM, DMA controller, event system, interrupt controller, and all peripherals to continue functioning. The power-down
mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI,
USB resume, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to
run, allowing the application to maintain a timer base while the rest of the device is sleeping. In standby mode, the
external crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the
external crystal, combined with low power consumption. In extended standby mode, both the main oscillator and the
asynchronous timer continue to run. To further reduce power consumption, the peripheral clock to each individual
peripheral can optionally be stopped in active mode and idle sleep mode.
Atmel offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR
microcontrollers.
The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory can
be reprogrammed in-system through the PDI or JTAG interfaces. A boot loader running in the device can use any
interface to download the application program to the flash memory. The boot loader software in the boot flash section will
continue to run while the application flash section is updated, providing true read-while-write operation. By combining an
8/16-bit RISC CPU with in-system, self-programmable flash, the AVR XMEGA is a powerful microcontroller family that
provides a highly flexible and cost effective solution for many embedded applications.
All Atmel AVR XMEGA devices are supported with a full suite of program and system development tools, including C
compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
XMEGA A3U [DATASHEET]
Atmel-8386D-AVR-ATxmega64A3U-128A3U-192A3U-256A3U–03/2014
4
Free Datasheet http://www.Datasheet4U.com

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ATXMEGA256A3U 전자부품, 판매, 대치품
6. AVR CPU
6.1 Features
8/16-bit, high-performance Atmel AVR RISC CPU
142 instructions
Hardware multiplier
32x8-bit registers directly connected to the ALU
Stack in RAM
Stack pointer accessible in I/O memory space
Direct addressing of up to 16MB of program memory and 16MB of data memory
True 16/24-bit access to 16/24-bit I/O registers
Efficient support for 8-, 16-, and 32-bit arithmetic
Configuration change protection of system-critical features
6.2 Overview
All Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and
perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the
program in the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and Programmable
Multilevel Interrupt Controller” on page 27.
6.3 Architectural Overview
In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories
and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to
be executed on every clock cycle. For details of all AVR instructions, refer to http://www.atmel.com/avr.
Figure 6-1. Block diagram of the AVR CPU architecture.
XMEGA A3U [DATASHEET]
Atmel-8386D-AVR-ATxmega64A3U-128A3U-192A3U-256A3U–03/2014
7
Free Datasheet http://www.Datasheet4U.com

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