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MT16JTF25664AZ 데이터시트 PDF




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부품번호 MT16JTF25664AZ 기능
기능 DDR3 SDRAM UDIMM
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MT16JTF25664AZ 데이터시트, 핀배열, 회로
2GB, 4GB, 8GB (x64, DR) 240-Pin DDR3 UDIMM
Features
DDR3 SDRAM UDIMM
MT16JTF25664AZ – 2GB
MT16JTF51264AZ – 4GB
MT16JTF1G64AZ – 8GB
Features
• DDR3 functionality and operations supported as per
component data sheet
• 240-pin, unbuffered dual in-line memory module
(UDIMM)
• Fast data transfer rates: PC3-14900, PC3-12800,
PC3-10600, PC3-8500, or PC3-6400
• 2GB (256 Meg x 64), 4GB (512 Meg x 64), 8GB (1 Gig x
64)
• VDD = VDDQ = 1.5V ±0.75V
• VDDSPD = 3.0–3.6V
• Reset pin for improved system stability
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• Dual rank
• 8 internal device banks for concurrent operation
• Fixed burst length (BL) of 8 and burst chop (BC) of 4
via the mode register
• Adjustable data-output drive strength
• Serial presence-detect (SPD) EEPROM
• Gold edge contacts
• Halogen-free
• Addresses are mirrored for second rank
• Fly-by topology
• Terminated control, command, and address bus
Figure 1: 240-Pin UDIMM (MO-269 R/C B)
Module height: 30.0mm (1.181in)
Options
• Operating temperature1
– Commercial (0°C TA +70°C)
– Industrial (–40°C TA +85°C)
• Package
– 240-pin DIMM (halogen-free)
• Frequency/CAS latency
– 1.07ns @ CL = 13 (DDR3-1866)
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.87ns @ CL = 7 (DDR3-1066)
Marking
None
I
Z
-1G9
-1G6
-1G4
-1G1
Note: 1. Contact Micron for industrial temperature
module offerings.
Table 1: Key Timing Parameters
Speed Industry
Grade Nomenclature
-1G9
PC3-14900
-1G6
PC3-12800
-1G4
PC3-10600
-1G1
PC3-8500
-1G0
PC3-8500
-80B
PC3-6400
CL =
13
1866
CL =
11
1600
1600
Data Rate (MT/s)
CL =
10 CL = 9 CL = 8 CL = 7
1333 1333 1066 1066
1333 1333 1066 1066
1333 1333 1066 1066
– – 1066 1066
– – 1066 –
––––
CL = 6
800
800
800
800
800
800
CL = 5
667
667
667
667
667
667
tRCD
(ns)
13.125
13.125
13.125
13.125
15
15
tRP
(ns)
13.125
13.125
13.125
13.125
15
15
tRC
(ns)
47.125
48.125
49.125
50.625
52.5
52.5
PDF: 09005aef837cdd2d
jtf16c256_512_1gx64az.pdf - Rev. H 09/12 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Free Datasheet http://www.Datasheet4U.com




MT16JTF25664AZ pdf, 반도체, 판매, 대치품
2GB, 4GB, 8GB (x64, DR) 240-Pin DDR3 UDIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR3
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 7: Pin Descriptions
Symbol
Ax
BAx
CKx,
CKx#
CKEx
DMx
ODTx
Par_In
RAS#, CAS#, WE#
RESET#
Sx#
SAx
SCL
CBx
DQx
DQSx,
DQSx#
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
(LVCMOS)
Input
Input
Input
I/O
I/O
I/O
Description
Address inputs: Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command.
Clock: Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DRAM.
Data mask (x8 devices only): DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write ac-
cess. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-
nation resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset: RESET# is an active LOW asychronous input that is connected to each DRAM
and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitial-
ized as though a normal power-up was executed.
Chip select: Enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs: Used to configure the temperature sensor/SPD EEPROM ad-
dress range on the I2C bus.
Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communi-
cation to and from the temperature sensor/SPD EEPROM on the I2C bus.
Check bits: Used for system error detection and correction.
Data input/output: Bidirectional data bus.
Data strobe: Differential data strobes. Output with read data; edge-aligned with
read data; input with write data; center-aligned with write data.
PDF: 09005aef837cdd2d
jtf16c256_512_1gx64az.pdf - Rev. H 09/12 EN
4 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
Free Datasheet http://www.Datasheet4U.com

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MT16JTF25664AZ 전자부품, 판매, 대치품
2GB, 4GB, 8GB (x64, DR) 240-Pin DDR3 UDIMM
DQ Map
Table 8: Component-to-Module DQ Map (Continued)
Component
Reference
Number
U10
U12
U14
U16
Component
DQ
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Module DQ
61
58
57
63
56
59
60
62
45
42
41
47
40
43
44
46
29
26
25
31
24
27
28
30
13
10
9
15
8
11
12
14
Module Pin
Number
228
114
109
234
108
115
227
233
210
96
91
216
90
97
209
215
150
36
31
156
30
37
149
155
132
18
13
138
12
19
131
137
Component
Reference
Number
U11
U13
U15
U17
Component
DQ
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Module DQ
53
50
49
55
48
51
52
54
37
34
33
39
32
35
36
38
21
18
17
23
16
19
20
22
5
2
1
7
0
3
4
6
Module Pin
Number
219
105
100
225
99
106
218
224
201
87
82
207
81
88
200
206
141
27
22
147
21
28
140
146
123
9
4
129
3
10
122
128
PDF: 09005aef837cdd2d
jtf16c256_512_1gx64az.pdf - Rev. H 09/12 EN
7 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
Free Datasheet http://www.Datasheet4U.com

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MT16JTF25664AZ

DDR3 SDRAM UDIMM

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