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ADF4351 데이터시트 PDF




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부품번호 ADF4351 기능
기능 Wideband Synthesizer
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ADF4351 데이터시트, 핀배열, 회로
Data Sheet
Wideband Synthesizer
with Integrated VCO
ADF4351
FEATURES
GENERAL DESCRIPTION
Output frequency range: 35 MHz to 4400 MHz
Fractional-N synthesizer and integer-N synthesizer
Low phase noise VCO
Programmable divide-by-1/-2/-4/-8/-16/-32/-64 output
Typical jitter: 0.3 ps rms
Typical EVM at 2.1 GHz: 0.4%
Power supply: 3.0 V to 3.6 V
Logic compatibility: 1.8 V
Programmable dual-modulus prescaler of 4/5 or 8/9
Programmable output power level
RF output mute function
3-wire serial interface
Analog and digital lock detect
Switched bandwidth fast lock mode
Cycle slip reduction
The ADF4351 allows implementation of fractional-N or integer-N
phase-locked loop (PLL) frequency synthesizers when used with
an external loop filter and external reference frequency.
The ADF4351 has an integrated voltage controlled oscillator (VCO)
with a fundamental output frequency ranging from 2200 MHz to
4400 MHz. In addition, divide-by-1/-2/-4/-8/-16/-32/-64 circuits
allow the user to generate RF output frequencies as low as 35 MHz.
For applications that require isolation, the RF output stage can be
muted. The mute function is both pin- and software-controllable.
An auxiliary RF output is also available, which can be powered
down when not in use.
Control of all on-chip registers is through a simple 3-wire interface.
The device operates with a power supply ranging from 3.0 V to
3.6 V and can be powered down when not in use.
APPLICATIONS
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX,
GSM, PCS, DCS, DECT)
Test equipment
Wireless LANs, CATV equipment
Clock generation
SDVDD
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VP RSET VVCO
REFIN
CLK
DATA
LE
×2
DOUBLER
10-BIT R
COUNTER
÷2
DIVIDER
DATA REGISTER
FUNCTION
LATCH
INTEGER FRACTION MODULUS
VALUE
VALUE
VALUE
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
N COUNTER
LOCK
DETECT
MULTIPLEXER
CHARGE
PUMP
PHASE
COMPARATOR
VCO
CORE
FAST LOCK
SWITCH
÷1/2/4/8/16/
32/64
OUTPUT
STAGE
OUTPUT
STAGE
MUXOUT
SW
LD
CPOUT
VTUNE
VREF
VCOM
TEMP
RFOUTA+
RFOUTA–
PDBRF
RFOUTB+
RFOUTB–
MULTIPLEXER
ADF4351
CE AGND
DGND
CPGND
Figure 1.
SDGND AGNDVCO
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
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ADF4351 pdf, 반도체, 판매, 대치품
ADF4351
Data Sheet
Parameter
Minimum RF Output Power3
Maximum RF Output Power3
Output Power Variation
Minimum VCO Tuning Voltage
Maximum VCO Tuning Voltage
NOISE CHARACTERISTICS
VCO Phase Noise Performance
Min
Normalized Phase Noise Floor
(PNSYNTH)4
Normalized 1/f Noise (PN1_f)5
In-Band Phase Noise
Integrated RMS Jitter6
Spurious Signals Due to PFD
Frequency
Level of Signal with RF Mute Enabled
Typ Max Unit Test Conditions/Comments
−4 dBm Programmable in 3 dB steps
5 dBm
±1 dB
0.5 V
2.5 V
−89
−114
−134
−148
−86
−111
−134
−145
−83
−110
−131
−145
−220
−221
−116
−118
−100
0.27
−80
−40
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps
dBc
dBm
VCO noise is measured in open-loop conditions
10 kHz offset from 2.2 GHz carrier
100 kHz offset from 2.2 GHz carrier
1 MHz offset from 2.2 GHz carrier
5 MHz offset from 2.2 GHz carrier
10 kHz offset from 3.3 GHz carrier
100 kHz offset from 3.3 GHz carrier
1 MHz offset from 3.3 GHz carrier
5 MHz offset from 3.3 GHz carrier
10 kHz offset from 4.4 GHz carrier
100 kHz offset from 4.4 GHz carrier
1 MHz offset from 4.4 GHz carrier
5 MHz offset from 4.4 GHz carrier
PLL loop BW = 500 kHz
ABP = 6 ns
ABP = 3 ns
10 kHz offset; normalized to 1 GHz
ABP = 6 ns
ABP = 3 ns
3 kHz from 2111.28 MHz carrier
1 ICP is internally modified to maintain constant loop gain over the frequency range.
2 TA = 25°C; AVDD = DVDD = VVCO = 3.3 V; prescaler = 8/9; fREFIN = 100 MHz; fPFD = 25 MHz; fRF = 4.4 GHz.
3 Using 50 Ω resistors to VVCO, into a 50 Ω load. Power measured with auxiliary RF output disabled. The current consumption of the auxiliary output is the same as for the
main output.
4 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log fPFD. To calculate in-band phase noise performance as seen at the VCO output, use the following formula: PNSYNTH = PNTOT − 10 log(fPFD) − 20 log N.
5 The PLL phase noise is composed of flicker (1/f) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF)
and at a frequency offset (f) is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
6 fREFIN = 122.88 MHz; fPFD = 30.72 MHz; VCO frequency = 4222.56 MHz; RFOUT = 2111.28 MHz; N = 137; loop BW = 60 kHz; ICP = 2.5 mA; low noise mode. The noise was
measured with an EVAL-ADF4351EB1Z and the Rohde & Schwarz FSUP signal source analyzer.
Rev. 0 | Page 4 of 28
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ADF4351 전자부품, 판매, 대치품
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADF4351
CLK 1
DATA 2
LE 3
CE 4
SW 5
VP 6
CPOUT 7
CPGND 8
PIN 1
INDICATOR
ADF4351
TOP VIEW
(Not to Scale)
24 VREF
23 VCOM
22 RSET
21 AGNDVCO
20 VTUNE
19 TEMP
18 AGNDVCO
17 VVCO
NOTES
1. THE LFCSP HAS AN EXPOSED PAD THAT
MUST BE CONNECTED TO GND.
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 CLK Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
2
DATA
Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high
impedance CMOS input.
3 LE
Load Enable. When LE goes high, the data stored in the 32-bit shift register is loaded into the register that is
selected by the three control bits. This input is a high impedance CMOS input.
4 CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.
A logic high on this pin powers up the device, depending on the status of the power-down bits.
5 SW
Fast Lock Switch. A connection should be made from the loop filter to this pin when using the fast lock mode.
6 VP
Charge Pump Power Supply. VP must have the same value as AVDD. Place decoupling capacitors to the ground
plane as close to this pin as possible.
7
8
9
10
11, 18, 21
12
CPOUT
CPGND
AGND
AVDD
AGNDVCO
RFOUTA+
Charge Pump Output. When enabled, this output provides ±ICP to the external loop filter. The output of the
loop filter is connected to VTUNE to drive the internal VCO.
Charge Pump Ground. This output is the ground return pin for CPOUT.
Analog Ground. Ground return pin for AVDD.
Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Place decoupling capacitors to the analog ground
plane as close to this pin as possible. AVDD must have the same value as DVDD.
VCO Analog Ground. Ground return pins for the VCO.
VCO Output. The output level is programmable. The VCO fundamental output or a divided-down version is
available.
13
RFOUTA−
Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided-
down version is available.
14
RFOUTB+
Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a divided-down
version is available.
15
RFOUTB−
Complementary Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a
divided-down version is available.
16, 17
19
VVCO
TEMP
Power Supply for the VCO. This pin ranges from 3.0 V to 3.6 V. Place decoupling capacitors to the analog
ground plane as close to these pins as possible. VVCO must have the same value as AVDD.
Temperature Compensation Output. Place decoupling capacitors to the ground plane as close to this pin as
possible.
20 VTUNE Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT
output voltage.
Rev. 0 | Page 7 of 28
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