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PDF AKD4186 Data sheet ( Hoja de datos )
| Número de pieza | AKD4186 | |
| Descripción | Low Power Touch Screen Controller | |
| Fabricantes | AKM | |
| Logotipo |  |
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[AK4186]
AK4186
Low Power Touch Screen Controller with I2C Interface
GENERAL DESCRIPTION
The AK4186 is a 4-wire/ 5-wire resistive touch screen controller that incorporates 12bit SAR A/D
converter. The AK4186 can detect the pressed screen location with two A/D conversions and it can also
measure touch pressure. The AK4186 has both an automatic continuous measurement and a
measurement data calculation function. The functions that normally require external processing, such
as calculating the average screen input value, are processed by the AK4186. In addition, a new
sequential mode achieves short coordinate measurement time while greatly reducing the
microprocessor overhead. The AK4186 operates off of supply voltage down to 1.6V in order to connect
a low voltage microprocessor. The AK4186 is the best fit for cellular phone, DSC, DVC, smart phone
and other portable devices.
FEATURES
! 4-wire or 5-wire Touch Screen Interface
! I2C Serial Interface
! 12bit SAR A/D Converter with S/H circuit
! Sampling Rate: 22.2kHz
! Pen Pressure Measurement (4-wire)
! Continuous Read Function
! Integrated Internal Osc (Sequence Mode)
! Integrated Median Averaging Filter
! Low Voltage Operation: VDD = 1.6V ~ 3.6V
! PENIRQN Buffer Output
! Low Power Consumption: 60µA at 1.8V
! Auto Power Down
! Package: 12pin CSP (1.7mm x 1.3mm, pitch 0.4mm)
16pin QFN (3mm x 3mm, pitch 0.5mm)
VDD
XP/BR
YP/TR
XN/TL
YN/BL
IN/
WIPER
MS1068-E-04
4/5wire
Touch
Screen
Drivers
Interface
MUX
VREF+
AIN+ SAR
ADC
AI N-
VREF-
VSS
Figure 1. Block Diagram
-1-
I2C
Serial I/F
&
Co ntro l
Lo gic
Internal
Osc
TEST
CAD0
SCL
SDA
PENIRQN
I2C-bus is a trademark of NXP B.V.
2011/03
Free Datasheet http://www.Datasheet4U.com
1 page  
[AK4186]
ANALOG CHARACTERISTICS
(Ta = -40°C to 85°C, VDD = 1.8V, I2C bus SCL=400kHz)
Parameter
min typ max Units
A/D Converter
Resolution
- 12 - Bits
No Missing Codes
11 12 - Bits
Integral Nonlinearity (INL) Error
- - ±2 LSB
Differential Nonlinearity (DNL) Error
-2 ±1 +3 LSB
Offset Error
AK4186ECB
- - ±6 LSB
AK4186EN
-4 - +8 LSB
Gain Error
AK4186ECB
- - ±4 LSB
AK4186EN
-4.5 - +3.5 LSB
Throughput Rate
- - 22.2 kHz
Touch Panel Drivers Switch On-Resistance
XP, YP
- 6 -Ω
XN, YN
- 6 -Ω
PENIRQ Pull Up Resistor RIRQ
Auxiliary IN Input
- 50 - kΩ
Input Voltage Range
0 - VDD V
Power Supply Current
Normal Mode (Single mode, PD0 bit = “0”)
VDD=1.8V
(Note 4) VDD=3.6V
-
-
60 - μA
- 220 μA
Normal Mode (Sequence mode, 10kHz equal rate) (Note 5)
- 25 - μA
Full Power Down (SDA = SCL = “H”)
- 0 3 μA
Note 4. Continuous ADC data read (fs = 22.2kHz). Expect for Power Consumption of Touch Panel driver.
Note 5. COUNT bit = “1”, INTERVAL2-0 bits = 000. Write command cycle = 1kHz. Expect for Power Consumption
of Touch Panel driver.
DC CHARACTERISTTICS (Logic I/O)
(Ta=-40°C to 85°C, VDD =1.6V to 3.6V)
Parameter
Symbol min
typ
“H” level input voltage
“L” level input voltage
Input Leakage Current
VIH 0.8xVDD
VIL -
IILK
-10
-
-
-
“H” level output voltage (PENIRQN pin @ Iout = -250μA) VOH VDD-0.3
-
“L” level output voltage (PENIRQN pin @ Iout = 250μA)
(SDA pin @ Iout = 3mA)
Tri-state Leakage Current (Note 6)
All pins expect for XP, YP, XN, YN pins
XP, YP, XN, YN pins
VOL
IOLK
-
-10
-10
-
Note 6. Expect for TEST pin. TEST pin has internal pull-down device, nominally 100kΩ.
max
-
0.2xVDD
10
-
0.3
10
10
Units
V
V
μA
V
V
μA
μA
MS1068-E-04
-5-
2011/03
Free Datasheet http://www.Datasheet4U.com
5 Page 
[AK4186]
■ Digital I/F
The AK4186 is controlled by a microprocessor via I2C bus and supports standard mode (100kHz) and fast mode
(400kHz). Note that the AK4186 operates in those two modes and does not support a High speed mode I2C-bus system
(3.4MHz). The AK4186 can operate as a slave device on the I2C bus network. The AK4186 operates off of supply
voltage down to 1.6V in order to connect a low voltage microprocessor.
4/5-wire touch panel
VDD=1.6V ~ 3.6V
AK4186
CAD0
Rp
“L” or “H”
Rp
SCL
SDA
PENIRQN
Micro-
Processor
I2C bus
Controller
Figure 6. Digital I/F
1. WRITE Operations
Figure 7 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates START condition (Figure 11). After the
START condition, a slave address is sent. This address is 6 bits long followed by the eighth bit that is a data direction
bit (R/W). The most significant five bits of the slave address are fixed as “100100”. The next bit is CAD0 (device
address bit). This bit identify the specific device on the bus. The hard-wired input pin (CAD0 pin) set this device
address bit (Figure 8). If the slave address matches that of the AK4186, the AK4186 generates an acknowledge and the
operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH)
during the acknowledge clock pulse (Figure 12). R/W bit value of “1” indicates that the read operation is to be executed.
“0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4186. The format is MSB first, and those most
significant two bits are fixed to zeros (Figure 9). The data after the second byte contains control data. The format is
MSB first, 8bits (Figure 10). The AK4186 generates an acknowledge after each byte is received. A data transfer is
always terminated by STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines STOP condition (Figure 11).
The AK4186 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4186
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating
the write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter
is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 1FH prior to
generating stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 13) except for the START and STOP conditions.
MS1068-E-04
- 11 -
2011/03
Free Datasheet http://www.Datasheet4U.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AKD4186.PDF ] | |
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