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PDF 93AA56C Data sheet ( Hoja de datos )
| Número de pieza | 93AA56C | |
| Descripción | 2K Microwire Compatible Serial EEPROM | |
| Fabricantes | Microchip | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 93AA56C (archivo pdf) en la parte inferior de esta página. Total 28 Páginas | ||
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93AA56A/B/C, 93LC56A/B/C,
93C56A/B/C
2K Microwire Compatible Serial EEPROM
Device Selection Table
Part Number VCC Range
93AA56A
93AA56B
93LC56A
93LC56B
93C56A
93C56B
93AA56C
93LC56C
93C56C
1.8-5.5
1.8-5-5
2.5-5.5
2.5-5.5
4.5-5.5
4.5-5.5
1.8-5.5
2.5-5.5
4.5-5.5
ORG Pin
No
No
No
No
No
No
Yes
Yes
Yes
Word Size
8-bit
16-bit
8-bit
16-bit
8-bit
16-bit
8 or 16-bit
8 or 16-bit
8 or 16-bit
Temp Ranges
I
I
I, E
I, E
I, E
I, E
I
I, E
I, E
Packages
P, SN, ST, MS, OT, MC
P, SN, ST, MS, OT, MC
P, SN, ST, MS, OT, MC
P, SN, ST, MS, OT, MC
P, SN, ST, MS, OT, MC
P, SN, ST, MS, OT, MC
P, SN, ST, MS, MC
P, SN, ST, MS, MC
P, SN, ST, MS, MC
Features:
• Low-power CMOS technology
• ORG pin to select word size for ‘56C’ version
• 256 x 8-bit organization ‘A’ ver. devices (no ORG)
• 128 x 16-bit organization ‘B’ ver. devices (no
ORG)
• Self-timed erase/write cycles (including
auto-erase)
• Automatic ERAL before WRAL
• Power-on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device Status signal (Ready/Busy)
• Sequential read function
• 1,000,000 E/W cycles
• Data retention > 200 years
• Pb-free and RoHS compliant
• Temperature ranges supported:
- Industrial (I)
-40°C to +85°C
- Automotive (E)
-40°C to +125°C
Pin Function Table
Name
Function
CS
CLK
DI
DO
VSS
NC
ORG
VCC
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
No internal connection
Memory Configuration
Power Supply
Description:
The Microchip Technology Inc. 93XX56A/B/C devices
are 2K bit low-voltage serial Electrically Erasable
PROMs (EEPROM). Word-selectable devices such as
the 93AA56C, 93LC56C or 93C56C are dependent
upon external logic levels driving the ORG pin to set
word size. For dedicated 8-bit communication, the
93XX56A devices are available, while the 93XX56B
devices provide dedicated 16-bit communication.
Advanced CMOS technology makes these devices
ideal for low-power, nonvolatile memory applications.
The entire 93XX Series is available in standard
packages including 8-lead PDIP and SOIC, and
advanced packaging including 8-lead MSOP, 6-lead
SOT-23, 8-lead 2x3 DFN and 8-lead TSSOP. All
packages are Pb-free and RoHS compliant.
© 2007 Microchip Technology Inc.
DS21794E-page 1
http://www.Datasheet4U.com
1 page  
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
FIGURE 1-1:
SYNCHRONOUS DATA TIMING
VIH
CS
VIL
VIH
CLK
VIL
TDIS
VIH
DI
VIL
TCSS
DO
(Read)
VOH
VOL
DO
(Program)
VOH
VOL
TSV
TCKH
TDIH
TPD
Note: TSV is relative to CS.
TCKL
Status Valid
TCSH
TPD
TCZ
TCZ
TABLE 1-3: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX56B OR 93XX56C WITH ORG = 1)
Instruction SB Opcode
Address
Data In Data Out Req. CLK Cycles
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
1 11 X A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)
1 00 1 0 X X X X X X — (RDY/BSY)
1 00 0 0 X X X X X X —
High-Z
1 00 1 1 X X X X X X —
High-Z
1 10 X A6 A5 A4 A3 A2 A1 A0 —
D15 – D0
1 01 X A6 A5 A4 A3 A2 A1 A0 D15 – D0 (RDY/BSY)
1 00 0 1 X X X X X X D15 – D0 (RDY/BSY)
11
11
11
11
27
27
27
TABLE 1-4: INSTRUCTION SET FOR X 8 ORGANIZATION (93XX56A OR 93XX56C WITH ORG = 0)
Instruction SB Opcode
Address
Data In Data Out
Req. CLK
Cycles
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
1
11 X A7 A6 A5 A4 A3 A2 A1 A0 —
(RDY/BSY)
1 00 1 0 X X X X X X X — (RDY/BSY)
1
00 0 0 X X X X X X X
—
High-Z
1
00 1 1 X X X X X X X
—
High-Z
1 10 X A7 A6 A5 A4 A3 A2 A1 A0 —
D7 – D0
1 01 X A7 A6 A5 A4 A3 A2 A1 A0 D7 – D0 (RDY/BSY)
1 00 0 1 X X X X X X X D7 – D0 (RDY/BSY)
12
12
12
12
20
20
20
© 2007 Microchip Technology Inc.
DS21794E-page 5
http://www.Datasheet4U.com
5 Page 
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
2.9 Write All (WRAL)
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
For 93AA56A/B/C and 93LC56A/B/C devices, after the
last data bit is clocked into DI, the falling edge of CS
initiates the self-timed auto-erase and programming
cycle. For 93C56A/B/C devices, the self-timed auto-
erase and programming cycle is initiated by the rising
edge of CLK on the last data bit. Clocking of the CLK
pin is not necessary after the device has entered the
WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction,
but the chip must be in the EWEN status.
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
Note:
After the Write All cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
VCC must be ≥ 4.5V for proper operation of WRAL.
FIGURE 2-10:
CS
WRAL TIMING FOR 93AA AND 93LC DEVICES
TCSL
CLK
DI 1 0 0 0 1 x ••• x Dx ••• D0
DO High-Z
VCC must be ≥ 4.5V for proper operation of WRAL.
TSV TCZ
Busy
TWL
Ready
High-Z
FIGURE 2-11:
CS
WRAL TIMING FOR 93C DEVICES
TCSL
CLK
DI 1 0 0 0 1 x ••• x Dx ••• D0
TSV TCZ
DO High-Z
Busy Ready
High-Z
TWL
© 2007 Microchip Technology Inc.
DS21794E-page 11
http://www.Datasheet4U.com
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet 93AA56C.PDF ] | |
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