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STFI20NK50Z
N-channel 500 V, 0.23 Ω, 17 A Zener-protected SuperMESH™
Power MOSFET in I²PAKFP package
Datasheet — production data
Features
Type
VDSS
STFI20NK50Z 500 V
RDS(on)
max
< 0.27 Ω
ID
17 A
PTOT
40 W
■ Fully insulated and low profile package with
increased creepage path from pin to heatsink
plate
■ Extremely high dv/dt capability
■ 100% avalanche tested
■ Gate charge minimized
Applications
■ Switching applications
Description
This device is an N-channel Zener-protected
Power MOSFET developed using
STMicroelectronics' SuperMESH™ technology,
achieved through optimization of ST's well-
established strip-based PowerMESH™ layout. In
addition to a significant reduction in on-
resistance, this device is designed to ensure a
high level of dv/dt capability for the most
demanding applications.
1
2
3
I2PAKFP
(TO-281)
Figure 1. Internal schematic diagram
D(2)
G(1)
S(3)
AM01476v1
Table 1. Device summary
Order codes
Marking
STFI20NK50Z
20NK50Z
Package
I2PAKFP
(TO-281)
Packaging
Tube
March 2012
This is information on a product in full production.
Doc ID 019007 Rev 3
1/13
www.st.com
13
http://www.Datasheet4U.com






Electrical characteristics
2 Electrical characteristics
STFI20NK50Z
(TCASE = 25 °C unless otherwise specified)
Table 5.
Symbol
On/off states
Parameter
Drain-source
V(BR)DSS breakdown voltage
(VGS = 0)
IDSS
Zero gate voltage
drain current (VGS = 0)
IGSS
Gate-body leakage
current (VDS = 0)
VGS(th) Gate threshold voltage
RDS(on)
Static drain-source on
resistance
Test conditions
ID =1 mA
VDS = 500 V
VDS = 500 V, TC = 125 °C
VGS = ± 20 V
VDS = VGS, ID = 100 µA
VGS = 10 V, ID = 8.5 A
Min. Typ. Max. Unit
500 V
1 µA
50 µA
± 10 µA
3 3.75 4.5 V
0.23 0.27 Ω
Table 6. Dynamic
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
gfs (1) Forward transconductance VDS = 15 V, ID = 8.5 A
Ciss
Coss
Crss
Input capacitance
Output capacitance
VDS = 25 V, f = 1 MHz,
Reverse transfer capacitance VGS = 0
Coss eq. (2)
Equivalent output
capacitance
VDS =0, VDS = 0 to 640 V
- 13
2600
- 328
72
- 187
S
pF
pF
pF
pF
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
VDD = 250 V, ID = 8.5 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 15)
28
20
-
70
15
ns
ns
ns
ns
Qg Total gate charge
Qgs Gate-source charge
Qgd Gate-drain charge
VDD = 400 V, ID = 17 A,
VGS = 10 V
(see Figure 16)
85 119 nC
- 15.5
nC
42 nC
1. Pulsed: pulse duration=300µs, duty cycle 1.5%
2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS.
4/13 Doc ID 019007 Rev 3
http://www.Datasheet4U.com

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STFI20NK50Z
Electrical characteristics
Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations
Figure 10. Normalized gate threshold voltage
vs temperature
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Figure 11. Normalized on resistance vs
temperature
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Figure 12. Maximum avalanche energy vs
temperature
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-;
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H9E/#"H
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Figure 13. Normalized BVDSS vs temperature
4H6EEH
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Doc ID 019007 Rev 3
7/13
http://www.Datasheet4U.com

7페이지