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ADSP-21469 데이터시트 PDF




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부품번호 ADSP-21469 기능
기능 SHARC Processor
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ADSP-21469 데이터시트, 핀배열, 회로
SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
5 Mbits of on-chip RAM, 4 Mbits of on-chip ROM
Up to 450 MHz operating frequency
Qualified for automotive applications, see Automotive Prod-
ucts on Page 70
Code compatible with all other members of the SHARC family
SHARC Processor
ADSP-21469
The ADSP-21469 processor is available with unique audio-
centric peripherals such as the digital applications
interface, DTCP (digital transmission content protection
protocol), serial ports, precision clock generators, S/PDIF
transceiver, asynchronous sample rate converters, input
data port, and more.
For complete ordering information, see Ordering Guide on
Page 70
SIMD Core
Instruction
Cache
5 Stage
Sequencer
DAG1/2
PEx
Timer
PEy
FLAGx/IRQx/
TMREXP
JTAG
THERMAL
DIODE
DMD
64-BIT
PMD
64-BIT
PERIPHERAL BUS
CORE PCG
FLAGS C-D
TIMER
1-0
TWI
SPI/B UART
DPI Routing/Pins
DPI Peripherals
Block 0
RAM/ROM
Internal Memory
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
S
Core Bus
Cross Bar
DMD
64-BIT
PMD 64-BIT
EPD BUS 64-BIT
B0D
64-BIT
B1D
64-BIT
B2D
64-BIT
Internal Memory I/F
IOD0 32-BIT
B3D
64-BIT
PERIPHERAL
BUS 32-BIT
IOD0 BUS
S/PDIF PCG
Tx/Rx A-D
ASRC PDAP/ SPORT
3-0 IDP 7-0
7-0
DAI Routing/Pins
DAI Peripherals
IOD1
32-BIT
FFT DTCP/
FIR MTM
IIR
SPEP BUS
LINK CORE PWM
MLB PORT FLAGS 3-0
1-0
EP
AMI DDR2
CTL
External Port Pin MUX
External
Port
Peripherals
Figure 1. Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Fax: 781.326.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.Datasheet4U.com




ADSP-21469 pdf, 반도체, 판매, 대치품
ADSP-21469
• Digital applications interface that includes four precision
clock generators (PCG), an input data port (IDP) for serial
and parallel interconnect, an S/PDIF receiver/transmitter,
four asynchronous sample rate converters, eight serial
ports, a flexible signal routing unit (DAI SRU).
• Digital peripheral interface that includes two timers, a 2-
wire interface, one UART, two serial peripheral interfaces
(SPI), 2 precision clock generators (PCG) and a flexible
signal routing unit (DPI SRU).
As shown in Figure 1 on Page 1, the processor uses two compu-
tational units to deliver a significant performance increase over
the previous SHARC processors on a range of DSP algorithms.
With its SIMD computational hardware, the processors can
perform 2.7 GFLOPS running at 450 MHz and 2.4 GFLOPS
running at 400 MHz.
FAMILY CORE ARCHITECTURE
The ADSP-21469 is code compatible at the assembly level with
the ADSP-2137x, ADSP-2136x, ADSP-2126x, ADSP-21160,
and ADSP-21161, and with the first generation ADSP-2106x
SHARC processors. The ADSP-21469 shares architectural fea-
tures with the ADSP-2126x, ADSP-2136x, ADSP-2137x, and
ADSP-2116x SIMD SHARC processors, as shown in Figure 2
and detailed in the following sections.
SIMD Computational Engine
The ADSP-21469 contains two computational processing
elements that operate as a single-instruction, multiple-data
(SIMD) engine. The processing elements are referred to as PEX
and PEY and each contains an ALU, multiplier, shifter, and
register file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both pro-
cessing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive DSP algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band-
width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
ments. These computation units support IEEE 32-bit single-
precision floating-point, 40-bit extended precision floating-
point, and 32-bit fixed-point data formats.
Timer
A core timer that can generate periodic software Interrupts. The
core timer can be configured to use FLAG3 as a timer expired
signal.
Data Register File
A general-purpose data register file is contained in each pro-
cessing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the processor’s enhanced Harvard
architecture, allow unconstrained data flow between computa-
tion units and internal memory. The registers in PEX are
referred to as R0-R15 and in PEY as S0-S15.
Context Switch
Many of the processor’s registers have secondary registers that
can be activated during interrupt servicing for a fast context
switch. The data registers in the register file, the DAG registers,
and the multiplier result registers all have secondary registers.
The primary registers are active at reset, while the secondary
registers are activated by control bits in a mode control register.
Universal Registers
These registers can be used for general-purpose tasks. The
USTAT (4) registers allow easy bit manipulations (Set, Clear,
Toggle, Test, XOR) for all system registers (control/status) of
the core.
The data bus exchange register (PX) permits data to be passed
between the 64-bit PM data bus and the 64-bit DM data bus, or
between the 40-bit register file and the PM/DM data buses.
These registers contain hardware to handle the data width
difference.
Single-Cycle Fetch of Instruction and Four Operands
The processors feature an enhanced Harvard Architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure 2). With the its separate program and data memory
buses and on-chip instruction cache, the processor can simulta-
neously fetch four operands (two over each data bus) and one
instruction (from the cache), all in a single cycle.
Instruction Cache
The processors contain an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Address Generators With Zero-Overhead Hardware
Circular Buffer Support
The two data address generators (DAGs) are used for indirect
addressing and implementing circular data buffers in hardware.
Circular buffers allow efficient programming of delay lines and
Rev. 0 | Page 4 of 72 | June 2010
Free Datasheet http://www.Datasheet4U.com

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ADSP-21469 전자부품, 판매, 대치품
FAMILY PERIPHERAL ARCHITECTURE
The ADSP-21469 family contains a rich set of peripherals that
support a wide variety of applications including high quality
audio, medical imaging, communications, military, test equip-
ment, 3D graphics, speech recognition, motor control, imaging,
and other applications.
External Port
The external port interface supports access to the external mem-
ory through core and DMA accesses. The external memory
address space is divided into four banks. Any bank can be pro-
grammed as either asynchronous or synchronous memory. The
external ports are comprised of the following modules.
• An Asynchronous Memory Interface which communicates
with SRAM, Flash, and other devices that meet the stan-
dard asynchronous SRAM access protocol. The AMI
supports 2M words of external memory in bank 0 and 4M
words of external memory in bank 1, bank 2, and bank 3.
• A DDR2 DRAM controller. External memory devices up to
2 Gbits in size can be supported.
• Arbitration Logic to coordinate core and DMA transfers
between internal and external memory over the external
port.
External Memory
The external port on the processor provides a high perfor-
mance, glueless interface to a wide variety of industry-standard
memory devices. The external port may be used to interface to
synchronous and/or asynchronous memory devices through the
use of its separate internal DDR2 memory controller. The 16-bit
DDR2 DRAM controller connects to industry-standard syn-
chronous DRAM devices, while the second 8-bit asynchronous
memory controller is intended to interface to a variety of mem-
ory devices. Four memory select pins enable up to four separate
devices to coexist, supporting any desired combination of syn-
chronous and asynchronous device types. Non-DDR2 DRAM
external memory address space is shown in Table 4.
Table 4. External Memory for Non-DDR2 DRAM Addresses
Bank
Bank 0
Bank 1
Bank 2
Bank 3
Size in
Words
2M
4M
4M
4M
Address Range
0x0020 0000 – 0x003F FFFF
0x0400 0000 – 0x043F FFFF
0x0800 0000 – 0x083F FFFF
0x0C00 0000 – 0x0C3F FFFF
SIMD Access to External Memory
The DDR2 controller on the ADSP-21469 processor supports
SIMD access on the 64-bit EPD (external port data bus) which
allows to access the complementary registers on the PEy unit in
the normal word space (NW). This improves performance since
there is no need to explicitly load the complimentary registers as
in SISD mode.
ADSP-21469
VISA and ISA Access to External Memory
The DDR2 controller on the ADSP-21469 processor supports
VISA code operation which reduces the memory load since the
VISA instructions are compressed. Moreover, bus fetching is
reduced because, in the best case, one 48-bit fetch contains three
valid instructions. Code execution from the traditional ISA
operation is also supported. Note that code execution is only
supported from bank 0 regardless of VISA/ISA. Table 5 shows
the address ranges for instruction fetch in each mode.
Table 5. External Bank 0 Instruction Fetch
Size in
Access Type Words
ISA (NW)
4M
VISA (SW) 10M
Address Range
0x0020 0000 - 0x005F FFFF
0x0060 0000 – 0x00FF FFFF
DDR2 Support
The ADSP-21469 supports a 16-bit DDR2 interface operating at
a maximum frequency of half the core clock. Execution from
external memory is supported. External memory devices up to
2 Gbits in size can be supported.
DDR2 DRAM Controller
The DDR2 DRAM controller provides a 16-bit interface to up to
four separate banks of industry-standard DDR2 DRAM devices.
Fully compliant with the DDR2 DRAM standard, each bank can
have its own memory select line (DDR2_CS3 – DDR2_CS0),
and can be configured to contain between 32M bytes and
256M bytes of memory. DDR2 DRAM external memory
address space is shown in Table 6.
A set of programmable timing parameters is available to config-
ure the DDR2 DRAM banks to support memory devices.
Table 6. External Memory for DDR2 DRAM Addresses
Bank
Bank 0
Bank 1
Bank 2
Bank 3
Size in
Words
62M
64M
64M
64M
Address Range
0x0020 0000 – 0x03FF FFFF
0x0400 0000 – 0x07FF FFFF
0x0800 0000 – 0x0BFF FFFF
0x0C00 0000 – 0x0FFF FFFF
Note that the external memory bank addresses shown are for
normal-word (32-bit) accesses. If 48-bit instructions, as well as
32-bit data, are both placed in the same external memory bank,
care must be taken while mapping them to avoid overlap.
Asynchronous Memory Controller
The asynchronous memory controller provides a configurable
interface for up to four separate banks of memory or I/O
devices. Each bank can be independently programmed with dif-
ferent timing parameters, enabling connection to a wide variety
Rev. 0 | Page 7 of 72 | June 2010
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ADSP-21469

SHARC Processor

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