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PDF PZ5032-10A44 Data sheet ( Hoja de datos )
| Número de pieza | PZ5032-10A44 | |
| Descripción | 32 Macrocell PLD | |
| Fabricantes | INTEGRATED CIRCUIT ENGINEERING | |
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Hay una vista previa y un enlace de descarga de PZ5032-10A44 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Construction Analysis
Philips PZ5032-10A44
32 Macrocell PLD
Report Number: SCA 9611-501
®
INTEGRATED CIRCUIT ENGINEERING CORPORATION
15022 N. 75th Street • Scottsdale, AZ 85260-2476
Telephone: 602-998-9780 • Fax: 602-948-1925
Free Datasheet http://www.Datasheet4U.com
1 page  
TECHNOLOGY DESCRIPTION (continued)
• Metallization consisted of three levels of metal. Each metal level consisted of
aluminum with titanium-nitride cap and barrier. Tungsten plugs were used to form
all vias and contacts.
• Interlevel dielectric consisted of four layers of silicon-dioxide with a planarizing
glass (probably SOG) layer in between glasses 2 and 4. An etchback was
performed prior to the deposition of the planarizing glass.
• Pre-metal dielectric consisted of a layer of reflow glass (probably BPSG) over
various densified oxides. The glass was reflowed prior to contact cuts only.
• A single layer of polycide (tungsten silicide) was used to form all gates on the die
and the top plates of all poly-to-diffusion capacitors. Direct poly-to-diffusion
(buried) contacts were not used. Definition was by a dry etch of normal quality.
• Standard implanted N+ and P+ diffusions formed the sources/drains of the CMOS
transistors. An LDD process was used with oxide sidewall spacers left in place.
Very light and shallow implants were present in the capacitor areas of the EEPROM
cells. Very thin tunnel oxide windows were used in these cells also.
• Local oxide (LOCOS) isolation was used. A step was present at the edge of the
well which indicates a twin-well process was used.
• A specialized 10T SRAM cell design was used as part of the programmable
elements. It employed the same process features as the rest of the die (at least to our
ability to detect). The process used for the EEPROM cells appeared to differ only in
the use of very thin tunnel oxide windows in the programming elements and a very
shallow lightly doped diffusion under the polycide in the capacitor storage elements
• Redundancy fuses were not present.
-3-
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5 Page 
OVERALL QUALITY EVALUATION: Overall Rating: Good.
DETAIL OF EVALUATION
Package integrity
Package markings
Die placement
Wirebond placement
Wire spacing
Wirebond quality
Die attach quality
Dicing quality
Die attach method
Dicing method
Wirebond method
Die surface integrity:
Toolmarks (absence)
Particles (absence)
Contamination (absence)
Process defects (absence)
General workmanship
Passivation integrity
Metal definition
Metal integrity
Metal registration
Contact coverage
Contact registration
N
N
N
N
N
N
N
N
Silver-filled polyimide
Sawn (full depth)
Thermosonic ball bonds using 1.2 mil gold wire.
G
G
G
G
G
G
N
N
G
G
G
G = Good, P = Poor, N = Normal, NP = Normal/Poor
-9-
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PZ5032-10A44.PDF ] | |
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