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기능 16-Output Switch
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33999 데이터시트, 핀배열, 회로
Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Document order number: MC33999
Rev 1.0, 01/2004
Preliminary Information
33999
16-Output Switch with SPI and PWM
Control
The 33999 is a 16-output low-side switch with a 24-bit serial input control.
It is designed for a variety of applications including inductive, incandescent,
and LED loads. The Serial Peripheral Interface (SPI) provides both input
control and diagnostic readout. Eight parallel inputs are also provided for direct
Pulse Width Modulation (PWM) control of eight dedicated outputs.
Additionally, an output-programmable PWM input provides PWM of any
combination of outputs. A dedicated reset input provides the ability to clear all
internal registers and turn all outputs off.
The 33999 directly interfaces with microcontrollers and is compatible with
both 3.3 V and 5.0 V CMOS logic levels. The 33999, in effect, serves as a bus
expander and buffer with fault management features that reduces the MCU’s
fault management burden.
Features
• Designed to Operate 5.0 V < VPWR < 27 V
• 24-Bit SPI for Control and Fault reporting, 3.3 V/5.0 V Compatible
• Outputs Are Current Limited (0.9 A to 2.5 A) to Drive Incandescent
Lamps
• Output Voltage Clamp of +50 V During Inductive Switching
• On/Off Control of Open Load Detect Current (LED Application)
• VPWR Standby Current < 10 µA
• RDS(ON) of 0.55 at 25°C Typical
• Independent Overtemperature Protection
• Output Selectable for PWM Control
• Output ON Short-to-VBAT and OFF Short-to-Ground/Open Detection
• 54-Pin Exposed Pad Package for Thermal Performance
• Pb-Free Packaging Designated by Suffix Code EK
POWER DUAL OCTAL SERIAL
SWITCH WITH SERIAL
PERIPHERAL INTERFACE I/O
EK (Pb-FREE) SUFFIX
CASE 1390-01
54-LEAD SOICW EXPOSED PAD
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
PC33999EK/R2 -40°C to 125°C 54 SOICW-EP
3339399999SiSmSiimmpplpliiffliiieefdideAdApppAlipcpalptiicolianctDaioitaingoranDmiDaigargarmam
3.3 V/5.0 V
33999
VPWR
VBAT
VDD
MCU
SCLK
CS
MISO
MOSI
PWM
RST
SOPWR
VPWR
SCLK
CS
SI
SO
PWM
RST
PWM0
PWM1
PWM6
PWM7
PWM8
PWM9
PWM14
PWM15
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
GND
Solenoid/Relay
LED
Lamp
This document contains information on a product under development.
Motorola reserves the right to change or discontinue this product without notice.
© Motorola, Inc. 2004
For More Information On This Product,
Go to: www.freescale.com
http://www.Datasheet4U.com/




33999 pdf, 반도체, 판매, 대치품
Freescale Semiconductor, Inc.
MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
VPWR Supply Voltage (Note 1)
VPWR
-1.5 to 50
V
SPI Interface Logic Supply Voltage (Note 1)
SOPWR
-0.3 to 7.0
V
SPI Interface Logic Input Voltage (CS, PWM, SI, SO, SCLK, RST, PWMn)
(Note 1)
VIN
-0.3 to 7.0
V
Output Drain Voltage
VDS
-0.3 to 45
V
Frequency of SPI Operation (Note 2)
fSPI 6.0 MHz
Output Clamp Energy (Note 3)
ECLAMP
50 mJ
ESD Voltage (Note 4)
Human Body Model (Note 5)
Machine Model (Note 6)
VESD1
VESD2
±2000
±200
V
Storage Temperature
TSTG
-55 to 150
°C
Operating Case Temperature
TC
-40 to 125
°C
Operating Junction Temperature
TJ
-40 to 150
°C
Power Dissipation (TA = 25°C) (Note 7)
PD 2.0 W
Lead Soldering Temperature (Note 8)
TSOLDER
260 °C
Thermal Resistance
Junction-to-Ambient (Note 9)
Junction-to-Case (Note 10)
Junction-to-Board
RθJA
RθJC
RθJB
°C/ W
60
1.2
8.0
Notes
1. Exceeding these limits may cause malfunction or permanent damage to the device.
2. This parameter is guaranteed by design but not production tested.
3. Maximum output clamp energy capability at 150°C junction temperature using single non-repetitive pulse method.
4. ESD data is available upon request.
5. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ).
6. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ).
7. Maximum power dissipation with no heat sink used.
8. Lead soldering temperature limit is for 10 seconds maximum duration. Not designed of immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
9. Tested per JEDEC test JESD52-2 (single-layer PWB).
10. Tested per JEDEC test JESD51-8 (two-layer PWB).
33999
4
For More Information OMnOTTOhRiOsLPA rAoNdAuLOcGt,INTEGRATED CIRCUIT DEVICE DATA
Go to: www.freescale.com
http://www.Datasheet4U.com/

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33999 전자부품, 판매, 대치품
Freescale Semiconductor, Inc.
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions of 3.1 V SOPWR 5.25 V, 9.0 V VPWR 16 V, -40°C TC 125°C, unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Slew Rate
RL = 56 (Note 16)
Output Turn ON Delay Time (Note 17)
SR V/µs
1.0 2.0 10
t DLY(on)
1.0
15
50 µs
Output Turn OFF Delay Time (Note 17)
t DLY(off)
1.0
15
50 µs
Output ON Short Fault Disable Report Delay (Note 18)
t DLY(short)
100
450 µs
Output OFF Open Fault Delay Time (Note 18)
t DLY(open)
100
450 µs
Output PWM Frequency
t FREQ
––
2.0 kHz
DIGITAL INTERFACE TIMING
Required Low State Duration on VPWR for Reset
VPWR 0.2 V (Note 19)
t RST
µs
– – 10
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
t LEAD
100
– ns
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
tLAG 50 –
– ns
SI to Falling Edge of SCLK (Required Setup Time)
t SI(su)
16
– ns
Falling Edge of SCLK to SI (Required Setup Time)
t SI(hold)
20
– ns
SI, CS, SCLK Signal Rise Time (Note 20)
t r (SI)
– 5.0 – ns
SI, CS, SCLK Signal Fall Time (Note 20)
t f (SI)
– 5.0 – ns
Time from Falling Edge of CS to SO Low Impedance (Note 21)
t SO (en)
– 50 ns
Time from Rising Edge of CS to SO High Impedance (Note 22)
t SO (dis)
– 50 ns
Time from Rising Edge of SCLK to SO Data Valid (Note 23)
t VALID – 25 80 ns
Notes
16. Output slew rate measured across a 56 resistive load.
17. Output turn ON and OFF delay time measured from 50% rising edge of CS to 90% and 10% of initial voltage.
18. Duration of fault before fault bit is set. Duration between access times must be greater than 450 µs to read faults.
19. This parameter is guaranteed by design but is not production tested.
20. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
21. Time required for valid output status data to be available on SO pin.
22. Time required for output status data to be terminated at SO pin.
23. Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
MOTOROLA ANALOG INTEGRATED CIRFCoUrITMDoErVeICEInDfAoTrAmation On This Product,
Go to: www.freescale.com
33999
7http://www.Datasheet4U.com/

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