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PDF ML9489 Data sheet ( Hoja de datos )
| Número de pieza | ML9489 | |
| Descripción | Static 1/2 Duty 1/3 Duty 1/4 Duty 160 Outputs LCD Driver | |
| Fabricantes | LAPIS | |
| Logotipo |  |
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ML9489
Static, 1/2 Duty, 1/3 Duty, 1/4 Duty 160 Outputs LCD Driver
FEDL9489-02
Issue Date: Apr. 3, 2013
GENERAL DESCRIPTION
The ML9489 is an LCD driver LSI, consists of a 160-bit shift register, a 640-bit data latch, 160 sets of LCD
drivers, and a common signal generation circuit.
It can directly drive an LCD up to 160 segments for static display, 320 segments for 1/2-duty display, 480
segments for 1/3-duty display, and 640 segments for 1/4-duty display.
The three-wire serial interface and I2C interface are selectable.
FEATURES
Logic power supply voltage : 2.7 to 5.5 V
LCD drive power supply voltage : 4.5 to 5.5 V
Maximum number of segments
Static display
: 160 segments
1/2-duty display
: 320 segments
1/3-duty display
: 480 segments
1/4-duty display
: 640 segments
Interface with microcomputer :
Serial interface : DATA, CLOCK, LOAD
CLOCK transfer speed up to 1 MHz
I2C interface : SDA, SCL, SDAACK
SCL transfer speed up to 400 kHz
Built-in CR oscillator circuit using the internal resistor or External resistor
Cascade connectable (up to eight chips)
Built-in common signal generation circuit
Built-in common output intermediate-value voltage generation circuit
Built-in POC (Power On Clear) circuit
Gold bump chip (ML9489DVWA)
Comparison table
Item ML
9479EDVWA
ML9489DVWA
Frame Frequency
65Hz/75Hz/85Hz/95Hz
130Hz/150Hz/170Hz/190Hz
(Internal oscillation) (programmable)
(programmable)
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1 page  
FEDL9489-02
ML9489
Switching Characteristics
OSC timing
Item
OSC IN clock frequency
(external input)
Clock pulse width
(External input)
Clock rise and fall time
(external input)
External Rf clock
frequency
(Internal oscillation)
Internal clock frequency
(Internal oscillation)
Symbol
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta = -40 to +105°C)
Condition
Min. Typ. Max. U nit Applicable pin
fCP1
Clock input from OSC1.
tWCP1 40 OSC2 and OSCR open.
OSC I/E = "L"
tOSC
— 1.8
10
——
— — (*1)
kHz OSC1
μs O SC1
μs O SC1
Between OSC1 and OSC2
fOSC1
Rf = 470kΩ
(F1,F0)=(0,1)
OSCR open.
18 28.8 44 kHz OSC1 , OSC2
OSC I/E = "H"
OSC1 open.
fOSC2
(F1,F0)=(0,1)
OSC2 and OSCR short-circuited.
18
28.8
44
kHz
OSC1, OSCR,
OSC2
OSC I/E = "H"
The relation between OSC IN clock frequency and frame frequency is as the equation below.
fFRM = fOSC /24
(*1) tOSC is a reference value.
The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value.
Make the rise as steep as possible. Reference value: max=2μs.
Serial interface timing
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta = -40 to +105°C)
Item
Symbol
Condition
Min. Typ. Max. Unit Applicable pin
Data clock frequency
fCP2
— — 1 MHz CLOCK
Data clock pulse width
tWCP2
100 — — ns CLOCK
Data setup time
tSU
50 — — ns DATA
Data hold time
tHD
50 — — ns CLOCK
CLOCK-LOAD timing
tCL
100 — — ns CLOCK
LOAD-CLOCK timing
tLC
100 — — ns LOAD
LOAD pulse width
tWLD
100 — — ns LOAD
Signal rise and fall time tsr,tsf
——
(*2)
ns
CLOCK,DATA,
LOAD
(*2) tsr and tsf shall be reference values.
The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value.
Make the rise as steep as possible. Reference value: max=10ns.
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5 Page 
FEDL9489-02
ML9489
98-102 SY NCB
105-108 I2C
36-40
DATA
(SDA)
41-45
CLOCK
(SCL)
46-50
LOAD
31-35
SDAACK
113-116 POCEB
73-77
RESETB
*3
Input/output pin for common synchronization. It has a schmitt circuit.
It be comes t he synchronization signal ou tput p in in the m aster m ode (M /S
I/O
pin = "H").
It becomes the synchronziation signal input pin in the slvae mode (M/S pin = "L").
For cascade connection, connect all of the i nvolved ML9489s' SYNC pins by
the common line.
Interface switching pin. It has a schmitt circuit.
I When this pin is "H", the interface is I2C.
When this pin is "L", the interface is three-wire serial.
Display data input pin. It has a schmitt circuit.
I2C="L": Serial interface; DATA
Input th e di splay data in t he order of SEG 160, SEG 159, ... , SEG 2, and
I
SEG1. The display data turns on at "H" and turns off at "L".
I2C="H": I2C interface; SDA
Input the display data in units of 8 bits. The display data turns on at "H" and
turns off at "L".
This pin has a built-in noise filter through which noises in widths up to 50 ns
are removed. This noise filter is valid only when I2C = "H".
Shift clock input pin for display data. It has a schmitt circuit.
I2C="L": Serial interface; CLOCK
The display data input to the DATA pin is serially input to the shift register at
I
the CLOCK signal rise.
I2C="H": I2C interface; SCL
The display data input to the SDA pin is serially input to the shift register at
the SCL signal rise.
This pin has a built-in noise filter through which noises in widths up to 50 ns
are removed. This noise filter is valid only when I2C = "H".
Input pin for the load signal of display data. It has a schmitt circuit.
I2C="L": Serial interface; LOAD
The display data in the shift register is transmitted as is to the segment driver
for the "H " duration. When t his pi n is br ought int o "L ", the shift re gister i s
I disconnected from the segment driv er. The display data in the shift re gister
immediately before it become "L" is held in the d ata latch and transmitted to
the segment driver.
I2C="H": I2C interface
Use this pin as it is connected to GND.
I2C="L": Serial interface
Use this pin as it is opened.
I2C="H": I2C interface
O T he I2C bus acknowledge output signal. Normally, use it as it is connected
with the SD A pin. C onnect an external pul l-up r esistor w henever
necessary, as it i s an ope n drain p in. The pul l-up connection des tination
supply voltage shall be the VDD supply voltage or less.
Internal POC circuit enable pin. It has a schmitt circuit.
When this pin is "H", the POC circuit becomes OFF and the constant current
I (8µA) is cut. The RESETB pin pull-up resistor is cut as well.
When this pin is "L", the POC circuit becomes ON.
The RESETB pin is connected to a pull-up resistor.
Reset s ignal in put p in for in itializing inside t he IC . It ha s a sch mitt cir cuit.
I
The "L" level enables the reset. This pin has an Internal pull-up resistor.
When POCEB = "H", input the external reset signal to this pin.
When POCEB = "L", the power-on reset operation is available by open this
pin.
11/32
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ML9489.PDF ] | |
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