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PDF 39VF010 Data sheet ( Hoja de datos )
| Número de pieza | 39VF010 | |
| Descripción | SST39VF010 | |
| Fabricantes | Silicon Storage Technology | |
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
SST39LF/VF512 / 010 / 020 / 0403.0 & 2.7V 512Kb / 1Mb / 2Mb / 4Mb (x8) MPF memories
FEATURES:
Data Sheet
• Organized as 64K x8 / 128K x8/ 256K x8 / 512K x8
• Single Voltage Read and Write Operations
– 3.0-3.6V for SST39LF512/010/020/040
– 2.7-3.6V for SST39VF512/010/020/040
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 10 mA (typical)
– Standby Current: 1 µA (typical)
• Sector-Erase Capability
– Uniform 4 KByte sectors
• Fast Read Access Time:
– 45 ns for SST39LF512/010/020/040
– 55 ns for SST39LF020/040
– 70 and 90 ns for SST39VF512/010/020/040
• Latched Address and Data
• Fast Erase and Byte-Program:
– Sector-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time:
1 second (typical) for SST39LF/VF512
2 seconds (typical) for SST39LF/VF010
4 seconds (typical) for SST39LF/VF020
8 seconds (typical) for SST39LF/VF040
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
– 48-ball TFBGA (6mm x 8mm) for 1 Mbit
PRODUCT DESCRIPTION
The SS T39LF512/010/020/040 an d S ST39VF512/010/
020/040 are 64K x8 , 128K x8, 256K x 8 an d 5124K x 8
CMOS Multi-Purpose F lash (MPF) manuf actured wit h
SST’s pr oprietary, hi gh p erformance CM OS S uperFlash
technology. The split-gate cell design and thick oxide tun-
neling injector attain better reliability and manufacturability
compared with alternate approaches. The SST39LF512/
010/020/040 devices write (Program or Erase) with a 3.0-
3.6V pow er su pply. The SS T39VF512/010/020/040
devices write with a 2.7-3.6V power supply. The devices
conform to JEDEC standard pinouts for x8 memories.
Featuring hi gh performance B yte-Program, th e
SST39LF512/010/020/040 a nd SST39VF512/010/020/
040 devices provide a maximum Byte-Program time of 20
µsec. These devices use Toggle Bit or Data# Polling to indi-
cate the co mpletion of Pr ogram op eration. T o pr otect
against inadvertent write, they have on-chip hardware and
Software Data P rotection s chemes. Designed, manufac-
tured, and tested for a wide spectrum of applications, they
are offered with a guaranteed endurance of 10,000 cycles.
Data retention is rated at greater than 100 years.
The SS T39LF512/010/020/040 an d S ST39VF512/010/
020/040 d evices ar e s uited f or ap plications th at r equire
convenient and economical updating of program, configu-
ration, or data memory. For all s ystem a pplications, they
significantly improves performance and reliability, while low-
ering power consumption. They inherently use less energy
during Erase and Program than alternative flash technolo-
gies. T he to tal en ergy c onsumed i s a f unction of th e
applied voltage, current, and time of application. Since for
any given voltage range, the SuperFlash technology uses
less current to program and has a shorter erase time, the
total energy consumed during any Erase or Program oper-
ation i s less than alternative fl ash te chnologies. T hese
devices also improve flexibility while lowering the cost for
program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To m eet s urface m ount r equirements, t he SST39LF512/
010/020/040 a nd SST39VF512/010/020/040 d evices a re
offered in 32-lead PLCC and 32-lead TSOP packages. The
39LF/VF010 is also offered in a 48-ball TFBGA package.
See Figures 1 and 2 for pinouts.
©2001 Silicon Storage Technology, Inc.
S71150-03-000 6/01
395
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
http://www.Datasheet4U.com
1 page  
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 SST39LF/VF512
A11
A9
A8
A13
A14
A17
WE#
VDD
A18
A16
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
A17
WE#
VDD
NC
A16
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
NC
WE#
VDD
NC
A16
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
NC
WE#
VDD
NC
NC
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Standard Pinout
Top View
Die Up
FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM)
SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040
32
OE#
OE#
OE#
31 A10 A10
A10
30 CE# CE# CE#
29
DQ7
DQ7
DQ7
28
DQ6
DQ6
DQ6
27
DQ5
DQ5
DQ5
26
DQ4
DQ4
DQ4
25
DQ3
DQ3
DQ3
24
VSS
VSS
VSS
23
DQ2
DQ2
DQ2
22
DQ1
DQ1
DQ1
21
DQ0
DQ0
DQ0
20 A0
A0
A0
19 A1
A1
A1
18 A2
A2
A2
17 A3
A3
A3
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
395 ILL F01.0
TOP VIEW (balls facing down)
SST39LF/VF010
6
A14 A13 A15 A16 NC NC NC VSS
5
A9 A8 A11 A12 NC A10 DQ6 DQ7
4
WE# NC NC NC DQ5 NC VDD DQ4
3
NC NC NC NC DQ2 DQ3 VDD NC
2
A7 NC A6 A5 DQ0 NC NC DQ1
1
A3 A4 A2 A1 A0 CE# OE# VSS
A BC D E F G H
FIGURE 3: PIN ASSIGNMENT FOR 48-BALL TFBGA (6MM X 8MM) FOR 1 MBIT
©2001 Silicon Storage Technology, Inc.
5
S71150-03-000 6/01 395
5 Page 
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
ADDRESS AMS-0
CE#
TAS
OE#
5555
TAH
TCP
2AAA
TCPH
5555
ADDR
INTERNAL PROGRAM OPERATION STARTS
TBP
TDH
TDS
WE#
TCH
DQ7-0
TCS
AA 55 A0 DATA
Note:
SW0
SW1
SW2
BYTE
(ADDR/DATA)
AMS = Most significant address
AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010,
A17 for SST39LF/VF020 and A18 for SST39LF/VF040
FIGURE 6: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
395 ILL F05.0
ADDRESS AMS-0
CE#
OE#
WE#
TOEH
TCE
TOE
DQ7
D D#
D#
Note:
AMS = Most significant address
AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010,
A17 for SST39LF/VF020 and A18 for SST39LF/VF040
FIGURE 7: DATA# POLLING TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
11
TOES
D
395 ILL F06.0
S71150-03-000 6/01 395
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet 39VF010.PDF ] | |
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