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PDF 3BS3LJ Data sheet ( Hoja de datos )
| Número de pieza | 3BS3LJ | |
| Descripción | ICE3BS03LJG | |
| Fabricantes | Infineon | |
| Logotipo |  |
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Version 2.0, 6 Dec 2007
F3 PWM controller
ICE3BS03LJG
Off-Line SMPS Current Mode
Controller with integrated 500V
Startup Cell ( Latched and
frequency jitter Mode )
Power Management & Supply
Never stop thinking.
http://www.Datasheet4U.com
1 page  
F3 PWM controller
ICE3BS03LJG
Pin Configuration and Functionality
1 Pin Configuration and Functionality
1.1 Pin Configuration with PG-DSO-8
1.2 Pin Functionality
Pin Symbol Function
1 BL extended Blanking and Latch off
enable
2 FB Feedback
3 CS Current Sense
4 Gate Gate driver output
5 HV High Voltage input
6 n.c. Not Connected
7 VCC Controller Supply Voltage
8 GND Controller Ground
BL (extended Blanking and Latch off enable)
The BL pin combines the fun ctions of extendable
blanking time for en tering the Auto Restart Protection
Mode and the external latch off enable. The extendable
blanking time func tion is to ex tend the built-in 2 0ms
blanking time by adding an external capacitor at BL to
ground. Th e external latch off enable func tion is an
external a ccess to la tch of f the IC . I t is tr iggered by
pulling down the BL pin to less than 0.25V.
FB (Feedback)
The information about the regulation is provided by the
FB Pin to the internal Protection Unit and to the internal
PWM-Comparator to control the d uty cycle. The F B-
Signal is the only co ntrol in case of light loa d at the
Active Burst Mode.
Package PG-DSO-8
BL 1
8 GND
CS (Current Sense)
The Current Sense pin se nses the v oltage developed
on the s eries res istor inse rted in th e so urce o f the
Power MOSFET. If CS reaches the internal th reshold
of the Current Limit Comp arator, the Drive r ou tput is
immediately switche d off. Furthermore, this c urrent
information ca n be u sed to re alize the Current Mode
operation through the PWM-Comp arator where it
compares with FB signal.
FB 2
CS 3
Gate
4
Gate
7 VCC The Gate pin is the output of the internal driver stage
connected to the Gate of an external power MOSFET.
6 N.C. HV (High Voltage)
5 HV
The high voltage Pin is connected to the rectified DC
input vo ltage. It is th e inp ut for the integrated 500V
Startup cell.
Figure 1
Pin Configuration PG-DSO-8(top view)
VCC (Power supply)
The VCC pin is the po sitive supply of the IC. The
operating range is between 10.5V and 26V.
GND (Ground)
The GND pin is the ground of the controller.
Version 2.0 5 6 Dec 2007
5 Page 
F3 PWM controller
ICE3BS03LJG
Functional Description
decrease gradually and the duty ratio of the gate drive
increases gr adually. The S oft S tart will be fin ished in
20ms (TSoft-Start) after the IC is switched on. At the end
of the Soft Start period, the current sink is switched off.
VSoftS
VSOFTS32
TSoft-Start
In add ition to Start-Up , So ft-Start is a lso ac tivated at
each restart attempt during Auto Restart.
The Start-Up time TStart-Up before the converter output
voltage VOUT is settled, mus t be shorter than the Soft-
Start Phase TSoft-Start (see Figure 13).
By means of Soft-Start ther e is an ef fective
minimization of c urrent a nd vo ltage stresses on th e
external power MOSFE T, the cla mp circ uit and th e
output overshoot and it helps to prev ent saturation of
the transformer during Start-Up.
Gate
Driver
3.5 PWM Section
0.75
t Oscillator
Duty Cycle
max
PWM Section
Clock
Frequency
t Jitter
Figure 12 Gate drive signal under Soft-Start Phase
Within the soft start period, the duty cycle is increasing
from zero to maximum gradually (see Figure 12).
VSoftS
VSOFTS32
TSoft-Start
Soft Start
Block
Soft Start
Comparator
PWM
Comparator
Current
Limiting
FF1
1S
Gate Driver
G8 R Q
&
G9
VFB
4.0V
VOUT
VOUT
TStart-Up
Figure 13 Start Up Phase
t
Figure 14 PWM Section Block
Gate
3.5.1
Oscillator
The oscillator generates a fixe d freq uency of 65KHz
with frequency jittering of ±4% (which is ±2.6KHz) at a
t jittering period of 4ms.
A capacitor, a current source and a current sink which
determine the frequency are integrated. The charging
and discharging current of the implem ented oscillator
capacitor are internally trimmed, in orde r to achieve a
very ac curate sw itching frequency. T he ratio of
controlled c harge to discharge c urrent is adjusted to
t reach a maximum duty cycle limitation of Dmax=0.75.
Once the Soft Start period is over and when the IC goes
into normal operating mode, the switching frequency of
the clock is v aried by the control signal from the So ft
Version 2.0 11 6 Dec 2007
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet 3BS3LJ.PDF ] | |
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