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AT86RF233 데이터시트 PDF




ATMEL Corporation에서 제조한 전자 부품 AT86RF233은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 AT86RF233 기능
기능 2.4GHz Transceiver
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AT86RF233 데이터시트, 핀배열, 회로
AT86RF233
Low Power, 2.4GHz Transceiver for ZigBee, RF4CE, IEEE
802.15.4, 6LoWPAN, and ISM Applications
PRELIMINARY DATASHEET
Features
High Performance RF-CMOS 2.4GHz radio transceiver targeted for IEEE® 802.15.4,
ZigBee®, RF4CE, 6LoWPAN, and ISM applications
Industry leading link budget:
Receiver sensitivity -101dBm
Programmable TX output power from -17dBm up to +4dBm
Ultra-low current consumption:
DEEP_SLEEP
= 0.02µA
TRX_OFF
= 300µA
RX_ON
= 11.8mA
(LISTEN)
Smart Receiving Techniques enable further current reduction in LISTEN mode
between 10 to 50% from 11.8mA
Desensitation will enable further reduction up to 1mA
BUSY_TX
= 13.8mA
(at max. transmit power)
Ultra-low supply voltage (1.8V to 3.6V) with internal regulator
Support for coin cell operation
Optimized for low BoM Cost and ease of production:
Few external components necessary (crystal, capacitors and antenna)
Easy to use interface:
Registers, frame buffer, and AES accessible through fast SPI
Only two microcontroller GPIO lines necessary
One interrupt pin from radio transceiver
Clock output with prescaler from radio transceiver
Radio transceiver features:
128-byte FIFO (SRAM) for data buffering
Fully integrated, fast settling PLL to support Frequency Hopping
Supports 500kHz channel spacing
Battery monitor and Fast Wake-Up Time < 0.4msec
Special IEEE 802.15.4™ 2011 hardware support:
FCS computation and Clear Channel Assessment
RSSI measurement, Energy Detection and Link Quality Indication
MAC hardware accelerator:
Automated acknowledgement, CSMA-CA and retransmission
Automatic address filtering
Automated FCS check
Extended feature set hardware support:
AES 128-bit hardware accelerator
Antenna Diversity and RX/TX indication
Supported PSDU data rates: 250kb/s, 500kb/s, 1000kb/s and 2000kb/s
True Random Number Generation for security application
Reduced Power Consumption modes
Time and phase measurement support
Industrial and extended temperature range:
-40°C to +85°C and -40°C to +125°C
I/O and packages:
32-pin Low-Profile QFN Package 5 x 5 x 0.9mm³
RoHS/Fully Green
Compliant to EN 300 328/440, FCC-CFR-47 Part 15, ARIB STD-66, RSS-210
Compliant to IEEE 802.15.4 2003/2006/2011
Atmel-8351E-MCU_Wireless-AT86RF233_Datasheet_072014




AT86RF233 pdf, 반도체, 판매, 대치품
9.3 Frame Buffer .......................................................................................................................................................... 118
9.3.1 Data Management ............................................................................................................................................................. 118
9.3.2 User accessible Frame Content......................................................................................................................................... 119
9.3.3 Interrupt Handling .............................................................................................................................................................. 119
9.4 Voltage Regulators (AVREG, DVREG) ................................................................................................................. 121
9.4.1 Overview............................................................................................................................................................................ 121
9.4.2 Configuration ..................................................................................................................................................................... 122
9.4.3 Data Interpretation ............................................................................................................................................................. 122
9.4.4 Register Description .......................................................................................................................................................... 122
9.5 Battery Monitor (BATMON).................................................................................................................................... 124
9.5.1 Overview............................................................................................................................................................................ 124
9.5.2 Configuration ..................................................................................................................................................................... 124
9.5.3 Data Interpretation ............................................................................................................................................................. 124
9.5.4 Interrupt Handling .............................................................................................................................................................. 125
9.5.5 Register Description .......................................................................................................................................................... 125
9.6 Crystal Oscillator (XOSC) ...................................................................................................................................... 127
9.6.1 Overview............................................................................................................................................................................ 127
9.6.2 Integrated Oscillator Setup ................................................................................................................................................ 127
9.6.3 External Reference Frequency Setup................................................................................................................................ 128
9.6.4 Master Clock Signal Output (CLKM).................................................................................................................................. 128
9.6.5 Register Description .......................................................................................................................................................... 129
9.7 Frequency Synthesizer (PLL) ................................................................................................................................ 132
9.7.1 Overview............................................................................................................................................................................ 132
9.7.2 RF Channel Selection........................................................................................................................................................ 132
9.7.3 PLL Settling Time and Frequency Agility ........................................................................................................................... 133
9.7.4 Calibration Loops............................................................................................................................................................... 133
9.7.5 Interrupt Handling .............................................................................................................................................................. 134
9.7.6 Register Description .......................................................................................................................................................... 134
9.8 Automatic Filter Tuning (FTN) ............................................................................................................................... 139
9.8.1 Overview............................................................................................................................................................................ 139
9.8.2 Register Description .......................................................................................................................................................... 139
10 Radio Transceiver Usage ....................................................................................................... 141
10.1 Frame Receive Procedure................................................................................................................................... 141
10.2 Frame Transmit Procedure.................................................................................................................................. 142
11 AT86RF233 Extended Feature Set ......................................................................................... 143
11.1 Security Module (AES) ........................................................................................................................................ 143
11.1.1 Overview.......................................................................................................................................................................... 143
11.1.2 Security Module Preparation ........................................................................................................................................... 143
11.1.3 Security Key Setup .......................................................................................................................................................... 144
11.1.4 Security Operation Modes ............................................................................................................................................... 144
11.1.5 Data Transfer – Fast SRAM Access ................................................................................................................................ 147
11.1.6 Start of Security Operation and Status ............................................................................................................................ 147
11.1.7 SRAM Register Summary................................................................................................................................................ 148
11.1.8 Register Description ........................................................................................................................................................ 148
11.2 Random Number Generator ................................................................................................................................ 151
11.2.1 Overview.......................................................................................................................................................................... 151
11.2.2 Register Description ........................................................................................................................................................ 151
11.3 High Data Rate Modes ........................................................................................................................................ 152
11.3.1 Overview.......................................................................................................................................................................... 152
11.3.2 High Data Rate Packet Structure..................................................................................................................................... 153
11.3.3 High Data Rate Frame Buffer Access.............................................................................................................................. 154
4 MCU Wireless AT86RF233 [PRELIMINARY DATASHEET]
Atmel-8351E-MCU_Wireless-AT86RF233_Datasheet_072014

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AT86RF233 전자부품, 판매, 대치품
1 Pin-out Diagram
Figure 1-1. Atmel AT86RF233 Pin-out Diagram.
DIG3
DIG4
AVSS
RFP
RFN
AVSS
DVSS
/RST
32 31 30 29 28 27 26 25
1 exposed paddle 24
2 AVSS
23
3 22
4
5
AT86RF233
21
20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
IRQ
/SEL
MOSI
DVSS
MISO
SCLK
DVSS
CLKM
Note:
1. The exposed paddle is electrically connected to the die inside the package. It
shall be soldered to the board to ensure electrical and thermal contact and good
mechanical stability.
MCU Wireless AT86RF233 [PRELIMINARY DATASHEET]
Atmel-8351E-MCU_Wireless-AT86RF233_Datasheet_072014
7

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