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기능 Novel Low Cost Green-Power PWM Controller
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H6850P 데이터시트, 핀배열, 회로
HI-SINCERITY
MICROELECTRONICS CORP.
Spec. No. : IC200912
Issued Date : 2009.07.15
Revised Date :
Page No. : 1/13
H6850 Series
Novel Low Cost Green-Power PWM Controller
With Low EMI Technique
Feature
z Low Cost, PWM&PFM&CRM (Cycle
Reset Mode)
z Low Start-up Current (about 3μA)
z Low Operating Current (about 1.2mA)
z Current Mode Operation
z Under Voltage Lockout (UVLO)
z Built-in Synchronized Slope
Compensation
z Built-in Low EMI Technique
z Programmable PWM Frequency
z Audio Noise Free Operation
z Leading edge Blanking on Sense input
z Constant output power limiting for
universal AC input Range
z SOT-23-6 L SOP8 and DIP-8 Pb-Free
Packaging
z Good Protection Coverage With Auto
Self-Recovery
z Compatible with SG6848 (6849) /
SG5701/SG5848/LD7535 (7550) /
OB2262 (2263)/OB22782279
z Complete Protection with
¾ Soft Clamped GATE output voltage
18.0V
¾ VDD over voltage protect 34.0V
¾ Cycle-by-cycle current limiting
¾ Output SCP (Short circuit Protection)
¾ Output OLP (Over Load Protection)
¾ High-Voltage CMOS Process with ESD
Applications
z Switching AC/DC Adaptor
z Battery Charger
z Open Frame Switching Power Supply
z Standby Power Supplies
z Set-Top Box Power Supplies
z 384X Replacement
General Description
The H68 50 is a highly integrated low cost
current mode PWM controller, which is ideal
for small power cur rent mode of of fline
AC-DC fly- back converter applic ations.
Making use of external resistors, the IC
changes the operating frequency and
automatically enters the PFM/CRM ( Cycle
Reset Mode) und er light-load/zer o-load
conditions. This can minimize standby
power consumption and achieve powe r-
saving functions. With a very lo w st art-up
current, the H685 0 could use a large value
start-up resistor (2M).
Built-in synchronized slo pe compens ation
enhances the st ability of the syste m and
avoids sub-harmonic oscillation. D ynamic
peak current limiting circuit minimizes output
power chang e caused by delay time of the
system over a universal AC input range.
Leading edge blanking circuit on current
sense input could remove the signal glitch
due to snubber circuit diode reverse
recovery and thus greatly reduces the
external component count and system cost
in the design. Cycle-by-Cycle current
limiting ensures safe operation even during
short-circuit.
Excellent EMI performance is achieved
built-in soft driver and low EMI technique.
The H68 50 offers perfect protection like
OVP(Over Voltage Prote ction)OLP(Over
Load Protection) SCP(Short circuit
protection)OTPSense Fault Protection
and OCP(Over current protection). The
H6850’s output driver is soft clamped to
maximum 18.0V to protect the power
MOSFET. H6850 is offered in SOT-23-6L,
SOT-8 and DIP-8 packages.
H6850P, H6850S,H6850NF
HSMC Product Specification
http://www.Datasheet4U.com




H6850P pdf, 반도체, 판매, 대치품
HI-SINCERITY
MICROELECTRONICS CORP.
Spec. No. : IC200804
Issued Date : 2008.09.19
Revised Date :
Page No. : 4/13
Electrical Characteristics (Ta=25°C unless otherwise noted, VDD = 16V)
Symbol
Parameter
Conditions Min. Typ. Max. Unit
Supply Voltage (VDD Pin)
IST Startup Current
ISS Operating Current
VDDON
VDDOFF
VDDCLAMP
VDDAIS
Turn-on Threshold Voltage
Turn-off Threshold Voltage
VDD Clamp Voltage
Anti Intermission Surge
VDD Voltage
VFB=0V
VFB=3V
VFB=Open
IVDD=10mA
3.0 20.0
3.0
1.2
0.8
13.0 14.0 15.0
7.8 8.8 9.8
34.0
μA
mA
mA
mA
V
V
V
9.4 V
Voltage Feedback (FB Pin)
IFB Short Circuit Current
VFB Open Loop Voltage
IFB_0D Zero Duty Cycle FB current
IPFM Enter PFM FB current
ICRM Enter CRM FB current
VPFM
Enter PFM Threshold VFB
VCRM Enter CRM Threshold VFB
IOLP&SCP Enter OLP&SCP FB current
VOLP&SCP Enter OLP&SCP FB voltage
TOLP&SCP OLP&SCP min. delay Time
VFB=0V
VFB=Open
RI=100K
Current Sensing (SEN Pin)
VTH_L
SEN Maximum Voltage Level
Dmin=0%
VTH_H
SEN Maximum Voltage
Level(Dmax=78%)
TPD Delay to Output
RI=100K,
FB=3.3V
RI=100K,
FB=3.3V
FB=3.3V
0.7 mA
4.8 V
0.59
mA
0.50
mA
0.55
mA
1.80 V
1.40 V
170 uA
3.7 V
33 35 50 mS
0.80
1.05
75
V
V
ns
H6850P, H6850S,H6850NF
HSMC Product Specification

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H6850P 전자부품, 판매, 대치품
HI-SINCERITY
MICROELECTRONICS CORP.
Spec. No. : IC200804
Issued Date : 2008.09.19
Revised Date :
Page No. : 7/13
To decrease the standby consumption
of the power supply, Chip-Rail introduces
the Cycle Reset Mode technology (CRM). If
the feedback current is over 0.59mA, mode
controller of the H6850 would reset internal
register all the time and cut off the GATE pin.
While the output voltage is lower than the
set value, the register would be set, the
GATE pin operate again. So the frequency
of the internal OSC is invariable, the register
would reset some pulses so that the
practical frequency is decreased at the
GATE pin.
Internal Synchronized Slop
Compensation
Although there are more advantages of
the current mode control than conventional
voltage mode control, there are still several
drawbacks of peak-sensing current-mode
converter, especially the open loop
instability when it operates in higher than
50% of the duty-cycle. To solve this problem,
the H6850 is introduced an internal slope
compensation adding voltage ramp to the
current sense input voltage for PWM
generation. It improves the close loop
stability greatly at CCM, prevents the
sub-harmonic oscillation and thus reduces
the output ripple voltage.
VSLOP
= 0.33× DUTY
DUTYMAX
= 0.4389 × DUTY
MOSFET comes into being a voltage VSENSE
on the Sense pin cycl e-by-cycle, which
compares to the internal reference volt age,
and control s the rever se of the internal
register, limits the peak current IMAX of the
primary of the transformer . The transforme r
energy is
E
=
1
2
×
L×
I MAX
2.
So
adjusting
the R SENSE can set the maximal o utput
power of the pow er su pple. The curre nt
flowing by the power MOSFET has an extra
value
( ΔI
= VIN
LP
× TD )
due
to
the
system
delay time that is from de tecting the current
through the Sense pin to power MOSFET off
in the H6850 (Among these, V IN is the
primary win ding volt age of the transformer
and L P is the primary wind inductance). V IN
ranges from 85V AC to 264V AC. To
guarantee the output power is a constant for
universal input AC voltage, there is a
dynamic peak limit circuit to compensate the
system delay T that the system delay brings
on.
Vsense
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
Duty Cycle
0% 10%20%30%40%50%60%70%80%90%
Slop Compensation
Current Sensing & Dynamic peak
limiting
The current flowing by the power
OLP&SCP
To protect the circuit from being
damaged under the over load or short circuit
condition, a smart OLP&SCP function is
implemented in the H6850. When short
circuit or over load occurs in the output end,
the feedback cycle would enhance the
voltage of FB pin, while the voltage is over
3.7V or the current from FB is below 170uA,
the internal detective circuit would send a
signal to shut down the GATE and pull down
the VDD voltage, then the circuit is restart.
To avoid the wrong operation when circuit
H6850P, H6850S,H6850NF
HSMC Product Specification

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