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PDF NB669 Data sheet ( Hoja de datos )
| Número de pieza | NB669 | |
| Descripción | 24V High Current Synchronous Buck Converter | |
| Fabricantes | MPS | |
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The Future of Analog IC Technology
NB669
24V, High Current
Synchronous Buck Converter With LDO
DESCRIPTION
The NB669 is a fully integrated hig h frequen cy
synchronous rectified step-d own s witch mode
converter with 5V fixed output voltage. It o ffers
very compact solution to achieve 6A continuous
output current and 9A peak output current over
a wide inpu t supply ra nge with e xcellent loa d
and line regulation. The NB669 operates at high
efficiency over a wide output current load range.
Constant-On-Time (COT ) co ntrol mode
provides fast transient response and eases loop
stabilization.
Under voltage lockout is internally set as 4.15 V.
An open drain po wer good signal indicates the
output is within its nominal voltage range.
NB669 also p rovides a 5V LDO, which can be
used to power the external peripheries, such as
the keyboard cont roller in the lapto p compute r.
A 300kHz CLK is also a vailable; its output can
be used to drive an external charge pump,
generating gate d rive voltage for the loa d
switches without redu cing the main converte r’s
efficiency.
Full protection feature s include OCP, OVP,
UVP and thermal shut down.
The converter requires minimum number of
external components and is availa ble in QFN16
(3mmx3mm) package.
TYPICAL APPLICATION
FEATURES
• Wide 6.5V to 24V Operating Input Range
• 5V Fixed Output Voltage
• Built-in 5V, 100mA LDO with Switches
• 6A Continuous Output Current
• 9A Peak Output Current
• 300kHZ CLK for External Charge Pump
• Lo w RDS(ON) Internal Power MOSFETs
• Proprietary Switching Loss Reduction
Technique
• Internal Soft Start
• Output Discharge
• 500kHZ Switching Frequency
• OCP, OVP, UVP Protection and Thermal
Shutdown
APPLICATIONS
• Laptop Computer
• Tablet PC
• Net working Systems
• Personal Video Recorders
• Flat Panel Television and Monitors
• Distributed Power Systems
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
NB669 Rev. 1.01
7/23/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
1
http://www.Datasheet4U.com
1 page  
NB669, 24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH LDO
PIN FUNCTIONS
PIN #
1 VIN
2
3
4 PG
5
6 LD
7 VO
8, 9
Exposed Pad
15, 16
10 BST
11 VC
12 EN
13 EN
14
Name
PGND
NC
CLK
O
UT
SW
C
LDO
AGND
Description
Supply Voltage. The VIN pin supplies power for internal MOSFET and regulator. The
NB669 operates from a +6.5V to +24V input rail. An input capacitor is needed to
decouple the input rail. Use wide PCB traces and multiple vias to make the
connection.
Power Ground. Use wide PCB traces and multiple vias to make the connection.
Not connected.
Power good output. The output of this pin is an open drain signal and is high if the
output voltage is higher than 95% of the nominal voltage. There is a delay from Vout
≥ 95% to PGOOD goes high.
300kHZ CLK output to drive the external charge pump
Internal 5V LDO output. Decouple with a minimum 4.7µF ceramic capacitor as close
to t he pin as p ossible. X7R or X5R gr ade dielectric c eramic c apacitors ar e
recommended for their stable temperature characteristics.
Once the output voltage of the Buck regulator is ready, it will switch over the LDO
output to save the power loss.
Output voltage sense. For the NB669, the output of the Buck regulator is fixed to 5V.
VOUT pin is used to sense the output voltage of the Buck regulator, connect this pin
to the output capacitor of the regulator directly. This pin also acts as the input of the
5V LDO switch over power input.
Keep the VO UT s ensing t race far away from t he S W n ode. Via s s hould als o b e
avoided on the VOUT sensing trace.
Switch Output. Connect this pin t o the inductor and bootstrap capacitor. This pin is
driven up to the VIN voltage by the high-side switch during the on-time of th e PWM
duty cycle. The inductor current drives the SW pin negative during the off-time. The
on-resistance of the l ow-side s witch and the i nternal diode fi xes t he negative
voltage. Use wide and short PCB traces to make the connection. Try to minimize the
area of the SW pattern.
Bootstrap. A c apacitor c onnected between S W a nd BST pins is required t o f orm a
floating supply across the high-side switch driver.
Internal 5V LDO output. The driver and control circuits are powered from this
voltage. Decouple with a minimum 1µF ceramic capacitor as close to the pin as
possible. X7R or X5R grade dielectric ceramic capacitors are recommended for their
stable temperature characteristics.
100mA LDO and VCC enable pin. ENLDO is in ternally pulled up to high. Leave this
pin open to enable the LDO. Drive it low to turn off all the regulators.
Buck regulator and charge pump clock enable pin. EN is a digital input that turns the
Buck r egulator a nd C LK on or off. W hen t he p ower s upply of t he c ontrol c ircuit is
ready, drive EN high t o t urn on t he Buck regulator and c harge pump c lock, dr ive it
low to turn them off.
Analog ground. The internal reference is referred to AGND.
NB669 Rev. 1.01
7/23/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
5
5 Page 
NB669, 24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH LDO
VNOISE
VS LOPE 2
V FB
V REF
Figure 3—Light Load Operation
As the output current in creases from the lig ht
load condit ion, the time period within which the
current mo dulator reg ulates becomes sho rter.
The HS -FET is turne d ON mo re frequently.
Hence, t he s witching freque ncy increases
correspondingly. The o utput cu rrent rea ches th e
critical le vel when the current modulator time is
zero. The critical le vel of the outp ut cu rrent is
determined as follows:
IOUT
=
(VIN −×VOUT) VOUT
2L×× FSW × VIN
(1)
It turns into PWM mode once the output curren t
exceeds the critical level. After that, the switching
frequency stays fairly c onstant over the output
current range.
Jitter and FB Ramp Slope
Jitter occurs in both PWM and skip modes when
noise in the V FB ripple propagate s a delay to th e
HS-FET d river, as sho wn in Figures 4 and 5 .
Jitter c an affect s ystem s tability, with nois e
immunity propor tional to the steep ness of V FB’s
downward slope. Ho wever, V FB rip ple does not
directly affect noise immunity.
VNOISE
V S L O PE1
VFB
VREF
HS D river
J itter
Figure 4—Jitter in PWM Mode
Jitter
HS D river
Figure 5—Jitter in Skip Mode
Selecting the Output Capacitors
The t raditional constan t-on-time co ntrol scheme
is intrinsica lly unstable if output capacitor’s ESR
is not large enough as an effective current-sense
resistor. Ce ramic capacitors usually can not be
used as output capacitor.
Figure 6 sho ws an e quivalent c ircuit in PW M
mode with the HS-FET off. To realize the stability,
the ESR value should be chosen as follow:
RESR
≥
TSTW
0.7 ×π
+
COUT
TSW is the switching period.
ON
2
(2)
L
SW
VOUT
R
FB
R
VOUT
ESR
CAP
Figure 6—Simplified Circuit in PWM Mode
The NB669 has built
in internal ramp
compensation to ma ke sure the system is stabl e
even without the help of output cap acitor’s ESR;
and thus the pure ce ramic capacitor solution can
be applicant. The pu re ceramic capacitor solution
can signif icantly reduce the output ripple, tot al
BOM cost and the board area.
Configuring the EN Control
The NB669 has t wo e nable pins t o control th e
on/off of the internal regulators.
ENLDO is used to en able or disable the whole
NB669 Rev. 1.01
7/23/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet NB669.PDF ] | |
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