PDF 2192VE Data sheet ( Hoja de datos )

Número de pieza	2192VE
Descripción	3.3VIn-SystemProgrammableSuperFASTHighDensityPLD
Fabricantes	LatticeSemiconductor
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No Preview Available ! ispLSI® 2192VE 3.3V In-System Programmable SuperFAST™ High Density PLD Features • SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 8000 PLD Gates — 96 I/O Pins, Nine or Twelve Dedicated Inputs — 192 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — Pinout Compatible with ispLSI 2096V and 2096VE • 3.3V LOW VOLTAGE ARCHITECTURE — Interfaces with Standard 5V TTL Devices • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 225MHz* Maximum Operating Frequency — tpd = 4.0ns* Propagation Delay — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power • IN-SYSTEM PROGRAMMABLE — 3.3V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP) — Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired- OR Bus Arbitration Logic — Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping • 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE • THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispDesignEXPERT™ – LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Functional Block Diagram Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 Output Routing Pool E7 E6 E5 E4 E3 E2 E1 E0 A0 A1 A2 A3 Global Routing Pool (GRP) A4 A5 A6 A7 DQ DQ Logic Array D Q GLB DQ D7 D6 D5 D4 D3 D2 D1 D0 B0 B1 B2 B3 B4 B5 B6 B7 Output Routing Pool C0 C1 C2 C3 C4 C5 C6 C7 Output Routing Pool 0139/2192VE Description The ispLSI 2192VE is a High Density Programmable Logic Device containing 192 Registers, nine or twelve Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2192VE features in-system programmability through the Bound- ary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2192VE offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable sys- tems. The basic unit of logic on the ispLSI 2192VE device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. F7 (see Figure 1). There are a total of 48 GLBs in the ispLSI 2192VE device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. *Preliminary Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com August 2000 2192ve_06 1 1 page Specifications ispLSI 2192VE External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST 3 COND. # DESCRIPTION1 -225 -180 UNITS MIN. MAX. MIN. MAX. tpd1 A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 4.0 – 5.0 ns tpd2 A 2 Data Propagation Delay – 6.2 – 7.5 ns fmax A 3 Clock Frequency with Internal Feedback 2 225 – 180 – MHz fmax (Ext.) fmax (Tog.) – 4 Clock Frequency with External Feedback (1 tsu2 + )tco1 – 5 Clock Frequency, Max. Toggle 150 – 125 – 250 – 200 – MHz MHz tsu1 – 6 GLB Reg. Setup Time before Clock, 4 PT Bypass 2.5 – 3.5 – ns tco1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass – 3.2 – 3.5 ns th1 – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – 0.0 – ns tsu2 – 9 GLB Reg. Setup Time before Clock 3.5 – 4.5 – ns tco2 A 10 GLB Reg. Clock to Output Delay – 3.7 – 4.5 ns th2 – 11 GLB Reg. Hold Time after Clock 0.0 – 0.0 – ns tr1 A 12 Ext. Reset Pin to Output Delay – 6.0 – 7.0 ns trw1 – 13 Ext. Reset Pulse Duration 3.5 – 4.0 – ns tptoeen B 14 Input to Output Enable – 6.0 – 10.0 ns tptoedis C 15 Input to Output Disable – 6.0 – 10.0 ns tgoeen B 16 Global OE Output Enable – 4.5 – 5.0 ns tgoedis C 17 Global OE Output Disable – 4.5 – 5.0 ns twh – 18 External Synchronous Clock Pulse Duration, High 2.0 – 2.5 – ns twl – 19 External Synchronous Clock Pulse Duration, Low 2.0 – 2.5 – ns 1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. Table 2-0030A/2192VE 5 5 Page Specifications ispLSI 2192VE Signal Descriptions Signal Name RESET GOE 0, GOE1 Y0, Y1, Y2 BSCAN TDI/IN 0 TCK/IN 7 TMS/IN 1 TDO/IN 6 IN 2-5, IN 8-11 GND VCC NC1 I/O Description Active Low (0) Reset pin resets all the registers in the device. Global Output Enable input pins. Dedicated Clock Input – These clock inputs are connected to one of the clock inputs of all the GLBs in the device. Input – Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. Input – This pin performs two functions. When BSCAN is logic low, it functions as a serial data input pin to load programming data into the device. When BSCAN is high, it functions as a dedicated input pin. Input – This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. Input – This pin performs two functions. When BSCAN is logic low, it functions as a mode control pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. Output/Input – This pin performs two functions. When BSCAN is logic low, it functions as an output pin to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin. Dedicated Input Pins to the device. Ground (GND) Vcc No Connect Input/Output Pins – These are the general purpose I/O pins used by the logic array. 1. NC pins are not to be connected to any active signals, VCC or GND. Signal Locations Signal Name 128-Pin TQFP 144-Ball fpBGA RESET 15 G4 GOE 0, GOE 1 80, 17 F12, G2 Y0, Y1, Y2 14, 83, 78 F3, F10, G11 BSCAN 19 F1 TDI/IN 0 20 G3 TMS/IN 1 48 J6 TDO/IN 6 112 C7 TCK/IN 7 77 G12 IN 2-5, IN 8-11 —, 49, 82, —, 84, 113, 13, — M7, J7, F9, G10, E12, B6, F2, E1 GND 18, 34, 50, 63, 79, 98, 111, 127 A1, A12, D4, D9, E5, E8, F6, F7, G6, G7, H5, H8, J4, J9, M1, M12 VCC 2, 16, 31, 47, 66, 81, 95, 114 B1, B12, E6, E7, F5, F8, G5, G8, H6, H7, L1, L12 NC1 — K2 1. NC pins are not to be connected to any active signals, VCC or GND. 11 11 Page

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