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CY14B116N 데이터시트 PDF




Cypress Semiconductor에서 제조한 전자 부품 CY14B116N은 전자 산업 및 응용 분야에서
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부품번호 CY14B116N 기능
기능 16-Mbit (2048 K x 8/1024 K x 16/512 K x 32) nvSRAM
제조업체 Cypress Semiconductor
로고 Cypress Semiconductor 로고


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CY14B116N 데이터시트, 핀배열, 회로
PRELIMINARY
CY14B116L/CY14B116N/CY14B116S
CY14E116L/CY14E116N/CY14E116S
16-Mbit (2048 K × 8/1024 K × 16/512 K × 32)
nvSRAM
Features
16-Mbit nonvolatile static random access memory (nvSRAM)
25-ns, 30-ns and 45-ns access times
Internally organized as 2048 K × 8 (CY14X116L),
1024 K × 16 (CY14X116N), 512 K × 32 (CY14X116S)
Hands-off automatic STORE on power-down with only a
small capacitor
STORE to QuantumTrap nonvolatile elements is initiated by
software, device pin, or AutoStore on power-down
RECALL to SRAM initiated by software or power-up
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years
Sleep mode operation
Low power consumption
Active current of 75 mA at 45 ns
Standby mode current of 650 A
Sleep mode current of 10 A
Operating voltages:
CY14B116X: VCC = 2.7 V to 3.6 V
CY14E116X: VCC = 4.5 V to 5.5 V
Industrial temperature: –40 C to +85 C
Packages
44-pin thin small-outline package (TSOP II)
48-pin thin small-outline package (TSOP I)
54-pin thin small-outline package (TSOP II)
165-ball fine-pitch ball grid array (FBGA) package
Restriction of hazardous substances (RoHS) compliant
Offered speeds
44-pin TSOP II: 25 ns and 45 ns
48-pin TSOP I: 30 ns and 45 ns
54-pin TSOP II: 25 ns and 45 ns
165-ball FBGA: 25 ns and 45 ns
Functional Description
The C ypress CY14X1 16L/CY14X116N/CY14X116S i s a fast
SRAM, with a no nvolatile el ement in each memory cel l. T he
memory is organized as 2048 K bytes of 8 bits each or 1024 K
words of 16 bits each o r 512 K words of 32 bit s each . T he
embedded non volatile elemen ts inco rporate Qu antumTrap
technology, prod ucing the world’s mo st reli able nonvolatile
memory. The SRAM can be read and written an infinite number
of times. The nonvolatile d ata residin g in the nonvolatile
elements do not change when data is written to the SRAM. Data
transfers from th e SRAM to the nonvolatile e lements (the
STORE operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from th e non volatile me mory. Both th e ST ORE an d RECALL
operations are also available under software control.
Errata: The engineering samples do not meet the address hold after end of write (tHA) and static discharge voltage specifications. For information on silicon errata, see
Errata on page 33. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-67793 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 1, 2014http://www.Datasheet4U.com




CY14B116N pdf, 반도체, 판매, 대치품
PRELIMINARY CY14B116L/CY14B116N/CY14B116S
CY14E116L/CY14E116N/CY14E116S
Pinouts
Figure 1. Pin Diagram: 44-Pin TSOP II (×8)
Figure 2. Pin Diagram: 54-Pin TSOP II (×16)
NC 1
A20 2
44 HSB
43 NC[6]
A0 3
A1 4
A2 5
A3 6
A4 7
CE 8
42 A19
41 A18
40 A17
39 A16
38 A15
37 OE
DQ0 9 44 - TSOP II 36 DQ7
DQ1 10
(x8)
35 DQ6
VCC
VSS
DQ2
11 34
12 Top View 33
13 (not to scale) 32
VSS
VCC
DQ5
DQ3 14
31 DQ4
WE 15
A5 16
30 VCAP
29 A14
A6 17
28 A13
A7 18
A8 19
A9 20
27 A12
26 A11
25 A10
NC 21
24 NC
NC 22
23 NC
NC
A19
A0
A1
A2
A3
A4
CE
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
WE
A5
A6
A7
A8
A9
NC
NC
NC
1 54
2 53
3 52
4 51
5 50
6 49
7 48
8 47
9 46
10 45
11 54 - TSOP II 44
12 (x16)
43
13 42
14 Top View 41
15 (not to scale) 40
16 39
17 38
18 37
19 36
20 35
21 34
22 33
23 32
24 31
25 30
26 29
27 28
HSB
A18
A17
A16
A15
OE
BHE
BLE
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ11
DQ10
DQ9
DQ8
VCAP
A14
A13
A12
A11
A10
NC
NC
NC
Figure 3. Pin Diagram: 48-Pin TSOP I (×8)
A15
A14
A13
A12
A11
A10
A9
A8
A19[5]
NC
WE
CE2
VCAP
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 - TSOP I
(x8)
Top View
(not to scale)
48 A16
47 HSB
46 VSS
45 A20
44 DQ7
43 NC
42 DQ6
41 NC
40 DQ5
39 NC
38 DQ4
37 VCC
36 NC
35 DQ3
34 NC
33 DQ2
32 NC
31 DQ1
30 NC
29 DQ0
28 OE
27 VSS
26 CE1
25 A0
Note
5. Address expansion for 32-Mbit. NC pin not connected to die.
Document #: 001-67793 Rev. *G
Page 4 of 38

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CY14B116N 전자부품, 판매, 대치품
PRELIMINARY CY14B116L/CY14B116N/CY14B116S
CY14E116L/CY14E116N/CY14E116S
Pin Definitions
Pin Name I/O Type
Description
A0 – A20
A0 – A19
A0 – A18
DQ0 – DQ7
Input
Address inputs. Used to select one of the 2,097,152 bytes of the nvSRAM for the ×8 configuration.
Address inputs. Used to select one of the 1,048,576 words of the nvSRAM for the ×16 configuration.
Address inputs. Used to select one of the 524,288 words of the nvSRAM for the ×32 configuration.
Bidirectional data I/O lines for the ×8 configuration. Used as input or output lines depending on
operation.
DQ0 – DQ15
Input/Output
Bidirectional data I/O lines for the ×16 configuration. Used as inpu t or output lines depending on
operation.
DQ0 – DQ31
Bidirectional data I/ O lin es for ×32 con figuration. U sed as in put or o utput li nes depending on
operation.
WE Inpu
t
Write Enable input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
address location.
CE
CE1, CE2
Input
Chip En able in put in TSOP II package, Active LOW. When LOW, selects the chip. When HIGH,
deselects the chip.
Chip Enable input in F BGA package. The device is sel ected and a memory access begins on the
falling edge of CE1 (while CE2 is HIGH) or the rising edge of CE2 (while CE1 is LOW).
OE
Input
Output Enable, Active LOW. The Active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the I/O pins to tristate.
BLE/BA[8]
BHE/BB[8]
BC[8]
BD[8]
ZZ[9]
Input
Input
Input
Input
Input
Byte Enable, Active LOW. When selected LOW, enables DQ7–DQ0.
Byte Enable, Active LOW. When selected LOW, enables DQ15–DQ8.
Byte Enable, Active LOW. When selected LOW, enables DQ23–DQ16.
Byte Enable, Active LOW. When selected LOW, enables DQ31–DQ24.
Sleep Mode Enable. When the ZZ pin is pulled LOW, the device enters a low-power Sleep mode and
consumes the lowest power. Since this input is logically AND’ed with CE, ZZ must be HIGH for normal
operation.
VCC
VSS
HSB
Power Supply Power supply inputs to the device.
Power Supply Ground for the device. Must be connected to ground of the system.
Input/Output
Hardware STORE Busy (HSB).When L OW, this ou tput indicates th at a Hard ware ST ORE is in
progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. After each
Hardware and Software STORE operation, HSB is driven HIGH for a short time (t HHHD) with standard
output high current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor
connection optional).
VCAP
Power Supply
AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
NC NC No Connect. Die pads are not connected to the package pin.
Notes
8. BLE, BHE are applicable for ×16 configuration and BA, BB, BC, BD are applicable for ×32 configuration only.
9. Sleep mode feature is offered in 165-ball FBGA package only.
Document #: 001-67793 Rev. *G
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관련 데이터시트

부품번호상세설명 및 기능제조사
CY14B116K

16-Mbit (2048 K x 8/1024 K x 16) nvSRAM

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CY14B116L

16-Mbit (2048 K x 8/1024 K x 16/512 K x 32) nvSRAM

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