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PDF AD9142 Data sheet ( Hoja de datos )
| Número de pieza | AD9142 | |
| Descripción | Digital-to-Analog Converter | |
| Fabricantes | Analog Devices | |
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Data Sheet
Dual, 16-Bit, 1600 MSPS, TxDAC+
Digital-to-Analog Converter
AD9142
FEATURES
Very small inherent latency variation: <2 DAC clock cycles
Proprietary low spurious and distortion design
6-carrier GSM ACLR = 79 dBc at 200 MHz IF
SFDR > 85 dBc (bandwidth = 300 MHz) at ZIF
Flexible 16-bit LVDS interface
Supports word and byte load
Multiple chip synchronization
Fixed latency and data generator latency compensation
Selectable 2×, 4×, 8× interpolation filter
Low power architecture
fS/4 power saving coarse mixer
Input signal power detection
Emergency stop for downstream analog circuitry
protection
FIFO error detection
On-chip numeric control oscillator allows carrier placement
anywhere in the DAC Nyquist bandwidth
Transmit enable function for extra power saving
High performance, low noise PLL clock multiplier
Digital gain and phase adjustment for sideband suppression
Digital inverse sinc filter
Supports single DAC mode
Low power: 2.0 W at 1.6 GSPS, 1.7 W at 1.25 GSPS, full
operating conditions
72-lead LFCSP
APPLICATIONS
Wireless communications: 3G/4G and MC-GSM base stations,
wideband repeaters, software defined radios
Wideband communications: point-to-point, LMDS/MMDS
Transmit diversity/MIMO
Instrumentation
Automated test equipment
GENERAL DESCRIPTION
The AD9142 is a dual, 16-bit, high dynamic range digital-to-
analog converter (DAC) that provides a sample rate of 1600 MSPS,
permitting a multicarrier generation up to the Nyquist frequency.
The AD9142 TxDAC+® includes features optimized for direct
conversion transmit applications, including complex digital mod-
ulation, input signal power detection, and gain, phase, and offset
compensation. The DAC outputs are optimized to interface
seamlessly with analog quadrature modulators, such as the
ADL537x F-MOD series and the ADRF670x series from Analog
Devices, Inc. A 3-wire serial port interface provides for the pro-
gramming/readback of many internal parameters. Full-scale
output current can be programmed over a range of 9 mA to 33 mA.
The AD9142 is available in a 72-lead LFCSP.
PRODUCT HIGHLIGHTS
1. Advanced low spurious and distortion design techniques
provide high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
2. Very small inherent latency variation simplifies both software
and hardware design in the system. It allows easy multichip
synchronization for most applications.
3. New low power architecture improves power efficiency
(mW/MHz/channel) by 30%.
4. Input signal power and FIFO error detection simplify
designs for downstream analog circuitry protection.
5. Programmable transmit enable function allows easy design
balance between power consumption and wakeup time.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices foritsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One T echnology Wa y, P .O. Box 9 106, Norwood, M A 02 062-9106, U .S.A.
Tel: 781.329.4700
©2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
http://www.Datasheet4U.com
1 page  
Data Sheet
AD9142
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Offset Error
Gain Error
Full-Scale Output Current
Output Compliance Range
Output Resistance
Gain DAC Monotonicity
Settling Time to Within ±0.5 LSB
MAIN DAC TEMPERATURE DRIFT
Offset
Gain
Reference Voltage
REFERENCE
Internal Reference Voltage
Output Resistance
ANALOG SUPPLY VOLTAGES
AVDD33
CVDD18
DIGITAL SUPPLY VOLTAGES
DVDD18
POWER CONSUMPTION
2× Mode
NCO OFF
NCO ON
4× Mode
NCO OFF
NCO ON
4× Mode
NCO OFF
NCO ON
8× Mode
NCO OFF
NCO ON
Phase-Lock Loop
Inverse Sinc
Reduced Power Mode (Power Down)
AVDD33
CVDD18
DVDD18
OPERATING RANGE
Test Conditions/Comments
With internal reference
Based on a 10 kΩ external resistor between FSADJ and AVSS
fDAC = 491.52 MSPS
fDAC = 737.28 MSPS
fDAC = 983.04 MSPS
fDAC = 1600 MSPS
fDAC = 1474.56 MSPS
Min Typ
16
Max
±2.1
±3.7
−0.001
−3.2
19.06
−1.0
0 +0.001
2 4.7
19.8 +20.6
+1.0
10
Guaranteed
20
0.04
100
30
1.17
5
1.19
3.13 3.3
1.71 1.8
3.47
1.89
1.71 1.8
1.89
700
870
836
1085
1030
1365
1315
1815
70
113
−40 +25
96.6
1.5
42.3
8.6
+85
Unit
Bits
LSB
LSB
% FSR
% FSR
mA
V
MΩ
ns
ppm/°C
ppm/°C
ppm/°C
V
kΩ
V
V
V
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mA
mA
mA
°C
Rev. 0 | Page 5 of 64
5 Page 
Data Sheet
AD9142
Pin No.
25
26
27
28
29
30
31
32
33
34
35
36
Mnemonic
D9N
D8P
D8N
DCIP
DCIN
D7P
D7N
D6P
D6N
D5P
D5N
DVDD18
37 D4P
38 D4N
39 D3P
40 D3N
41 D2P
42 D2N
43 DVDD18
44 D1P
45 D1N
46 D0P
47 D0N
48 DVDD18
49 DVDD18
50 IRQ2
51 IRQ1
52 SDIO
53 SCLK
54 CS
55 AVDD33
56 IOUT2P
57 IOUT2N
58 AVDD33
59 CVDD18
60 CVDD18
61 DACCLKN
62 DACCLKP
63 CVDD18
64 CVDD18
65 AVDD33
66 IOUT1N
67 IOUT1P
68 AVDD33
69 FSADJ
70 REFIO
71 CVDD18
72 CVDD18
EPAD
Description
Data Bit 9, Negative.
Data Bit 8, Positive.
Data Bit 8, Negative.
Data Clock Input, Positive.
Data Clock Input, Negative.
Data Bit 7, Positive.
Data Bit 7, Negative.
Data Bit 6, Positive.
Data Bit 6, Negative.
Data Bit 5, Positive.
Data Bit 5, Negative.
1.8 V Digital Supply. Pin 36 supplies power to the digital core, digital data ports, serial port input/output pins,
RESET, IRQ1, and IRQ2.
Data Bit 4, Positive.
Data Bit 4, Negative.
Data Bit 3, Positive.
Data Bit 3, Negative.
Data Bit 2, Positive.
Data Bit 2, Negative.
1.8 V Digital Supply. Pin 43 supplies power to the digital core, digital data ports, serial port input/output pins,
RESET, IRQ1, and IRQ2.
Data Bit 1, Positive.
Data Bit 1, Negative.
Data Bit 0 (LSB), Positive.
Data Bit 0 (LSB), Negative.
1.8 V Digital Supply. Pin 48 supplies power to the digital core, digital data ports, serial port input/output pins,
RESET, IRQ1, and IRQ2.
1.8 V Digital Supply. Pin 49 supplies power to the digital core, digital data ports, serial port input/output
pins, RESET, IRQ1, and IRQ2.
Second Interrupt Request. Open-drain, active low output. Connect an external pull-up to DVDD18 through a 10 kΩ resistor.
First Interrupt Request. Open-drain, active low output. Connect an external pull-up to DVDD18 through a 10 kΩ resistor.
Serial Port Data Input/Output. CMOS levels with respect to DVDD18.
Serial Port Clock Input. CMOS levels with respect to DVDD18.
Serial Port Chip Select. Active low (CMOS levels with respect to DVDD18).
3.3 V Analog Supply.
QDAC Positive Current Output.
QDAC Negative Current Output.
3.3 V Analog Supply.
1.8 V Clock Supply. Supplies clock receivers and clock distribution.
1.8 V Clock Supply. Supplies clock receivers and clock distribution.
DAC Clock Input, Negative.
DAC Clock Input, Positive.
1.8 V Clock Supply. Supplies clock receivers and clock distribution.
1.8 V Clock Supply. Supplies clock receivers and clock distribution.
3.3 V Analog Supply.
IDAC Negative Current Output.
IDAC Positive Current Output.
3.3 V Analog Supply.
Full-Scale Current Output Adjust. Place a 10 kΩ resistor from this pin to AVSS.
Voltage Reference. Nominally 1.2 V output. Decouple REFIO to AVSS.
1.8 V Clock Supply. Pin 71 supplies the clock receivers, clock multiplier, and clock distribution.
1.8 V Clock Supply. Pin 72 supplies the clock receivers, clock multiplier, and clock distribution.
Exposed Pad. The exposed pad (EPAD) must be soldered to the ground plane (AVSS). The EPAD provides an
electrical, thermal, and mechanical connection to the board.
Rev. 0 | Page 11 of 64
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9142.PDF ] | |
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