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AT45DB321E 데이터시트 PDF




Adesto에서 제조한 전자 부품 AT45DB321E은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 AT45DB321E 기능
기능 2.3V Minimum SPI Serial Flash Memory
제조업체 Adesto
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AT45DB321E 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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AT45DB321E 데이터시트, 핀배열, 회로
AT45DB321E
32-Mbit DataFlash (with Extra 1-Mbits), 2.3V Minimum
SPI Serial Flash Memory
Features
Single 2.3V - 3.6V supply
Serial Peripheral Interface (SPI) compatible
Supports SPI modes 0 and 3
Supports RapidSoperation
Continuous read capability through entire array
Up to 85MHz
Low-power read option up to 15MHz
Clock-to-output time (tV) of 6ns maximum
User configurable page size
512 bytes per page
528 bytes per page (default)
Page size can be factory pre-configured for 512 bytes
Two fully independent SRAM data buffers (512/528 bytes)
Flexible programming options
Byte/Page Program (1 to 512/528 bytes) directly into main memory
Buffer Write
Buffer to Main Memory Page Program
Flexible erase options
Page Erase (512/528 bytes)
Block Erase (4KB)
Sector Erase (64KB)
Chip Erase (32-Mbits)
Program and Erase Suspend/Resume
Advanced hardware and software data protection features
Individual sector protection
Individual sector lockdown to make any sector permanently read-only
128-byte, One-Time Programmable (OTP) Security Register
64 bytes factory programmed with a unique identifier
64 bytes user programmable
Hardware and software controlled reset options
JEDEC Standard Manufacturer and Device ID Read
Low-power dissipation
400nA Ultra-Deep Power-Down current (typical)
3µA Deep Power-Down current (typical)
25µA Standby current (typical)
11mA Active Read current (typical)
Endurance: 100,000 program/erase cycles per page minimum
Data retention: 20 years
Green (Pb/Halide-free/RoHS compliant) packaging options
8-lead SOIC (0.208" wide)
8-pad Ultra-thin DFN (5 x 6 x 0.6mm)
9-ball Ultra-thin UBGA (6 x 6 x 0.6mm)
Die in Wafer Form
8784G–DFLASH–7/2015




AT45DB321E pdf, 반도체, 판매, 대치품
2. Block Diagram
Figure 2-1. Block Diagram
WP
Page (512/528 bytes)
Flash Memory Array
SCK
CS
RESET
VCC
GND
Buffer 1 (512/528 bytes)
Buffer 2 (512/528 bytes)
I/O Interface
SI SO
AT45DB321E
8784G–DFLASH–7/2015
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AT45DB321E 전자부품, 판매, 대치품
the device will continue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum
SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array
Read bypasses the data buffers and leaves the contents of the buffers unchanged.
Warning: This command is not recommended for new designs.
5.2 Continuous Array Read (High Frequency Mode: 1Bh Opcode)
This command can be used to read the main memory array sequentially at the highest possible operating clock
frequency up to the maximum specified by fCAR4. To perform a Continuous Array Read using the standard DataFlash
page size (528 bytes), the CS pin must first be asserted, and then an opcode of 1Bh must be clocked into the device
followed by three address bytes and two dummy bytes. The first 13 bits (PA12 - PA0) of the 23-bit address sequence
specify which page of the main memory array to read and the last 10 bits (BA9 - BA0) of the 23-bit address sequence
specify the starting byte address within the page. To perform a Continuous Array Read using the binary page size (512
bytes), the opcode 1Bh must be clocked into the device followed by three address bytes (A21 - A0) and two dummy
bytes. Following the dummy bytes, additional clock pulses on the SCK pin will result in data being output on the SO
(Serial Output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of
data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue
reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover
from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read,
the device will continue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum
SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array
Read bypasses both data buffers and leaves the contents of the buffers unchanged.
5.3 Continuous Array Read (High Frequency Mode: 0Bh Opcode)
This command can be used to read the main memory array sequentially at higher clock frequencies up to the maximum
specified by fCAR1. To perform a Continuous Array Read using the standard DataFlash page size (528 bytes), the CS pin
must first be asserted, and then an opcode of 0Bh must be clocked into the device followed by three address bytes and
one dummy byte. The first 13 bits (PA12 - PA0) of the 23-bit address sequence specify which page of the main memory
array to read and the last 10 bits (BA9 - BA0) of the 23-bit address sequence specify the starting byte address within the
page. To perform a Continuous Array Read using the binary page size (512 bytes), the opcode 0Bh must be clocked into
the device followed by three address bytes (A21 - A0) and one dummy byte. Following the dummy byte, additional clock
pulses on the SCK pin will result in data being output on the SO pin.
The CS pin must remain low during the loading of the opcode, the address bytes, the dummy byte, and the reading of
data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue
reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover
from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read,
the device will continue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum
SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array
Read bypasses both data buffers and leaves the contents of the buffers unchanged.
5.4 Continuous Array Read (Low Frequency Mode: 03h Opcode)
This command can be used to read the main memory array sequentially at lower clock frequencies up to maximum
specified by fCAR2. Unlike the previously described read commands, this Continuous Array Read command for the lower
AT45DB321E
8784G–DFLASH–7/2015
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