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24AA65 데이터시트 PDF




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부품번호 24AA65 기능
기능 64K 1.8V I2C Smart Serial EEPROM
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24AA65 데이터시트, 핀배열, 회로
24AA65
64K 1.8V I2CSmart SerialEEPROM
FEATURES
• Voltage operating range: 1.8V to 6.0V
- Peak write current 3 mA at 6.0V
- Maximum read current 150 µA at 6.0V
- Standby current 1 µA typical
• Industry standard two wire bus protocol I2C
compatible
• 8 byte page, or byte modes available
• 2 ms typical write cycle time, byte or page
• 64-byte line input cache for fast write loads
• Up to 8 devices may be connected to the same
bus for up to 512K bits total memory
• 100 kHz (1.8V) and 400 kHz (5.0V) compatibility
• Programmable block security options
• Programmable endurance options
• Schmitt trigger, filtered inputs for noise suppres-
sion
• Output slope control to eliminate ground bounce
• Self-timed ERASE and WRITE cycles
• Power on/off data protection circuitry
• Endurance:
- 10,000,000 E/W cycles guaranteed for a High
Endurance Block
- 1,000,000 E/W cycles guaranteed for a Stan-
dard Endurance Block
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP/SOIC packages
• Temperature ranges
- Commercial (C):
0°C to +70°C
DESCRIPTION
The Microchip Technology Inc. 24AA65 is a “smart” 8K x
8 Serial Electrically Erasable PROM. This device has
been developed for advanced, low power applications
such as personal communications, and provides the
systems designer with flexibility through the use of many
new user-programmable features. It is capable of opera-
tion down to 1.8V, the end-of-life voltage for 2 “AA” bat-
tery cells for most popular battery technologies.The
24AA65 offers a relocatable 4K bit block of ultra-high-
endurance memory for data that changes frequently. The
remainder of the array, or 60K bits, is rated at 1,000,000
ERASE/WRITE (E/W) cycles guaranteed. The 24AA65
features an input cache for fast write loads with a capac-
ity of eight pages, or 64 bytes. This device also features
programmable security options for E/W protection of crit-
ical data and/or code of up to fifteen 4K blocks. Func-
tional address lines allow the connection of up to eight
I2C is a trademark of Philips Corporation.
Smart Serial is a trademark of Microchip Technology Inc.
PACKAGE TYPES
PDIP
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 NC
6 SCL
5 SDA
SOIC
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 NC
6 SCL
5 SDA
BLOCK DIAGRAM
A0..A2
HV Generator
I/O
Control
Logic
I/O SCL
SDA
Vcc
Vss
Memory
Control
Logic
XDEC
EEPROM ARRAY
Page Latches
Buffer
YDEC
Sense AMP
R/W Control
24LC65's on the same bus for up to 512K bits contigu-
ous EEPROM memory. Advanced CMOS technology
makes this device ideal for low-power non-volatile code
and data applications. The 24AA65 is available in the
standard 8-pin plastic DIP and 8-pin surface mount
SOIC package.
© 1996 Microchip Technology Inc.
DS21056F-page 1
This document was created with FrameMaker 4 0 4




24AA65 pdf, 반도체, 판매, 대치품
24AA65
2.0 FUNCTIONAL DESCRIPTION
The 24AA65 supports a bidirectional two-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus must be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24AA65 works
as slave. Both master and slave can operate as trans-
mitter or receiver but the master device determines
which mode is activated.
3.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1 Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2 Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3 Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4 Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.
3.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note:
The 24AA65 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave (24AA65) must leave the data line HIGH to
enable the master to generate the STOP condition.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A) (B) (D) (D)
SCL
SDA
START
CONDITION
ADDRESS OR
DATA
ACKNOWLEDGE ALLOWED
VALID
TO CHANGE
(C) (A)
STOP
CONDITION
DS21056F-page 4
© 1996 Microchip Technology Inc.

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24AA65 전자부품, 판매, 대치품
5.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
5.1 Current Address Read
The 24AA65 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n (n is
any legal address), the next current address read oper-
ation would access data from address n + 1. Upon
receipt of the slave address with R/W bit set to one, the
24AA65 issues an acknowledge and transmits the eight
bit data word. The master will not acknowledge the
transfer but does generate a stop condition and the
24AA65 discontinues transmission (Figure 4-3).
5.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24AA65 as part of a write operation (R/W bit set to 0).
After the word address is sent, the master generates a
start condition following the acknowledge. This termi-
nates the write operation, but not before the internal
address pointer is set. Then the master issues the con-
trol byte again but with the R/W bit set to a one. The
24AA65 will then issue an acknowledge and transmit
the eight bit data word. The master will not acknowl-
edge the transfer but does generate a stop condition
which causes the 24AA65 to discontinue transmission
(Figure 4-4).
5.3 Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24AA65 transmits the
first data byte, the master issues an acknowledge as
opposed to the stop condition used in a random read.
This acknowledge directs the 24AA65 to transmit the
next sequentially addressed 8 bit word (Figure 4-5).
Following the final byte transmitted to the master, the
master will NOT generate an acknowledge but will gen-
erate a stop condition.
To provide sequential reads the 24AA65 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
24AA65
5.4 Contiguous Addressing Across
Multiple Devices
The device select bits A2, A1, A0 can be used to
expand the contiguous address space for up to 512K
bits by adding up to eight 24LC65's on the same bus.
In this case, software can use A0 of the control byte as
address bit A13, A1 as address bit A14, and A2 as
address bit A15.
5.5 Noise Protection
The SCL and SDA inputs have filter circuits which sup-
press noise spikes to assure proper device operation
even on a noisy bus. All I/O lines incorporate Schmitt
triggers for 400 kHz (Fast Mode) compatibility.
5.6 High Endurance Block
The location of the high-endurance block within the
memory map is programmed by setting the leading bit
7 (S/HE) of the configuration byte to 0. The upper bits
of the address loaded in this command will determine
which 4K block within the memory map will be set to
high endurance. This block will be capable of
10,000,000 ERASE/WRITE cycles (Figure 8-1).
Note:
The High Endurance Block cannot be
changed after the security option has been
set. If the H.E. block is not programmed by
the user, the default location is the highest
block of memory.
5.7 Security Options
The 24AA65 has a sophisticated mechanism for write-
protecting portions of the array. This write protect func-
tion is programmable and allows the user to protect 0-
15 contiguous 4K blocks. The user sets the security
option by sending to the device the starting block num-
ber for the protected region and the number of blocks to
be protected. If the security option is invoked with 0
blocks protected, then all portions of the array will be
unprotected. All parts will come from the factory in the
default configuration with the starting block number set
to 15 and the number of protected blocks set to zero.
THE SECURITY OPTION CAN BE SET ONLY ONCE.
To invoke the security option, a write command is sent
to the device with the leading bit (bit 7) of the first
address byte set to a 1 (Figure 8-1). Bits 1-4 of the first
address byte define the starting block number for the
protected region. For example, if the starting block
number is to be set to 5, the first address byte would be
1XX0101X. Bits 0, 5 and 6 of the first address byte are
disregarded by the device and can be either high or low.
The device will acknowledge after the first address
byte. A byte of don't care bits is then sent by the master,
with the device acknowledging afterwards. The third
byte sent to the device has bit 7 (S/HE) set high and bit
6 (R) set low. Bits 4 and 5 are don't cares and bits 0-3
define the number of blocks to be write protected. For
example, if three blocks are to be protected, the third
© 1996 Microchip Technology Inc.
DS21056F-page 7

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부품번호상세설명 및 기능제조사
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64K I2C Serial EEPROM

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