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PDF 24C01 Data sheet ( Hoja de datos )

Número de pieza 24C01
Descripción 2-WireSerialEEPROM
Fabricantes ATMELCorporation 
Logotipo ATMELCorporation Logotipo



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Features
Low Voltage and Standard Voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 2.5 (VCC = 2.5V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
Internally Organized 128 x 8
2-Wire Serial Interface
Bidirectional Data Transfer Protocol
100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility
4-Byte Page Write Mode
Self-Timed Write Cycle (10 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
– ESD Protection: >3000V
Automotive Grade and Extended Temperature Devices Available
8-Pin PDIP, 8-Pin MSOP, 8-Pin TSSOP and 8-Pin JEDEC SOIC Packages
Description
The AT24C01 provides 1024 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 128 words of 8 bits each. The device is
optimized for use in many industrial and commercial applications where low power
and low voltage operation are essential. The AT24C01 is available in space saving
8-pin PDIP, 8-pin MSOP, 8-pin TSSOP, and 8-pin JEDEC SOIC packages and is
accessed via a 2-wire serial interface. In addition, the entire family is available in 5.0V
(4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) ver-
sions.
2-Wire Serial
EEPROM
1K (128 x 8)
AT24C01
Pin Configurations
Pin Name
NC
SDA
SCL
Test
Function
No Connect
Serial Data
Serial Clock Input
Test Input (GND or VCC)
NC
NC
NC
GND
8-Pin MSOP
8-Pin TSSOP
18
27
36
45
VCC
TEST
SCL
SDA
2-Wire, 1K
Serial EEPROM
8-Pin PDIP
NC
NC
NC
GND
1
2
3
4
8 VCC
7 TEST
6 SCL
5 SDA
8-Pin SOIC
NC
NC
NC
GND
1
2
3
4
8 VCC
7 TEST
6 SCL
5 SDA
Rev. 0134C–07/98
1

1 page




24C01 pdf
Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
AT24C01
Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
8th BIT ACK
WORD n
STOP
CONDITION
tWR(1)
START
CONDITION
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write
cycle.
5

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