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24C02A-ESL 데이터시트 PDF




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부품번호 24C02A-ESL 기능
기능 1K/2K/4K 5.0V I2C Serial EEPROMs
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24C02A-ESL 데이터시트, 핀배열, 회로
24C01A/02A/04A
1K/2K/4K 5.0V I2CSerial EEPROMs
FEATURES
• Low power CMOS technology
• Hardware write protect
• Two wire serial interface bus, I2Ccompatible
• 5.0V only operation
• Self-timed write cycle (including auto-erase)
• Page-write buffer
• 1ms write cycle time for single byte
• 1,000,000 Erase/Write cycles guaranteed
• Data retention >200 years
• 8-pin DIP/SOIC packages
• Available for extended temperature ranges
- Commercial (C):
- Industrial (I):
- Automotive (E):
0˚C to +70˚C
-40˚C to +85˚C
-40˚C to +125˚C
DESCRIPTION
The Microchip Technology Inc. 24C01A/02A/04A is a
1K/2K/4K bit Electrically Erasable PROM. The device
is organized as shown, with a standard two wire serial
interface. Advanced CMOS technology allows a signif-
icant reduction in power over NMOS serial devices. A
special feature in the 24C02A and 24C04A provides
hardware write protection for the upper half of the block.
The 24C01A and 24C02A have a page write capability
of two bytes and the 24C04A has a page length of eight
bytes. Up to eight 24C01A or 24C02A devices and up
to four 24C04A devices may be connected to the same
two wire bus.
This device offers fast (1ms) byte write and
extended (-40°C to 125°C) temperature operation. It
is recommended that all other applications use
Microchip’s 24LCXXB.
Organization
Write Protect
Page Write
Buffer
24C01A
128 x 8
None
2 Bytes
24C02A
258 x 8
080-0FF
2 Bytes
24C04A
2 x 256 x 8
100-1FF
8 Bytes
PACKAGE TYPES
DIP A0 1
A1 2
A2 3
VSS 4
8-lead
SOIC A0
A1
A2
VSS
1
2
3
4
14-lead
SOIC
NC
A0
A1
NC
1
2
3
4
A2 5
VSS 6
NC 7
* “TEST” pin in 24C01A
BLOCK DIAGRAM
Vcc
Vss
SDA
Data
Buffer
(FIFO)
Data Reg.
Slave Addr.
SCL
Control
Logic
I2C is a trademark of Philips Corporation.
A0 A1 A2 WP
© 1996 Microchip Technology Inc.
This document was created with FrameMaker 4 0 4
8 VCC
7 WP*
6 SCL
5 SDA
8 VCC
7 WP*
6 SCL
5 SDA
14 NC
13 VCC
12 WP
11 NC
10 SCL
9 SDA
8 NC
Vpp R/W Amp
AP
do
di
rn
et
se
A0 to
A7
sr
Memory
Array
Increment
A8
DS11183D-page 1




24C02A-ESL pdf, 반도체, 판매, 대치품
24C01A/02A/04A
2.0 FUNCTIONAL DESCRIPTION
The 24C01A/02A/04A supports a bidirectional two wire
bus and data transmission protocol. A device that
sends data onto the bus is defined as transmitter, and
a device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions, while the
24C01A/02A/04A works as slave. Both master and
slave can operate as transmitter or receiver but the
master device determines which mode is activated.
Up to eight 24C01/24c02s can be connected to the bus,
selected by the A0, A1 and A2 chip address inputs. Up
to four 24C04As can be connected to the bus, selected
by A1 and A2 chip address inputs. A0 must be tied to
VCC or VSS for the 24C04A. Other devices can be con-
nected to the bus but require different device codes
than the 24C01A/02A/04A (refer to section Slave
Address).
3.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1 Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2 Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3 Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4 Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.
3.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note:
The 24C01A/02A/04A does not generate
any acknowledge bits if an internal pro-
gramming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A) (B) (D) (D)
SCL
SDA
START
CONDITION
ADDRESS OR
DATA
ACKNOWLEDGE ALLOWED
VALID
TO CHANGE
(C) (A)
STOP
CONDITION
DS11183D-page 4
© 1996 Microchip Technology Inc.

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24C02A-ESL 전자부품, 판매, 대치품
24C01A/02A/04A
8.0 WRITE PROTECTION
Programming of the upper half of the memory will not
take place if the WP pin of the 24C02A or 24C04A is
connected to VCC (+5.0V). The device will accept slave
and word addresses but if the memory accessed is
write protected by the WP pin, the 24C02A/04A will not
generate an acknowledge after the first byte of data has
been received, and thus the program cycle will not be
started when the STOP condition is asserted. Polarity
of the WP pin has no effect on the 24C01A.
9.0 READ MODE
This mode illustrates master device reading data from
the 24C01A/02A/04A.
As can be seen from Figure 9-2 and Figure 9-3, the
master first sets up the slave and word addresses by
doing a write. (Note: Although this is a read mode, the
address pointer must be written to). During this period
the 24C01A/02A/04A generates the necessary
acknowledge bits as defined in the appropriate section.
The master now generates another START condition
and transmits the slave address again, except this time
the read/write bit is set into the read mode. After the
slave generates the acknowledge bit, it then outputs
the data from the addressed location on to the SDA pin,
increments the address pointer and, if it receives an
acknowledge from the master, will transmit the next
consecutive byte. This auto-increment sequence is
only aborted when the master sends a STOP condition
instead of an acknowledge.
Note 1: If the master knows where the address
pointer is, it can begin the read sequence
at the current address (Figure 9-1) and
save time transmitting the slave and word
addresses.
Note 2: In all modes, the address pointer will not
increment through a block (256 byte)
boundary, but will rotate back to the first
location in that block.
FIGURE 9-1: CURRENT ADDRESS READ
S
BUS ACTIVITY
MASTER
T
A
R
CONTROL
BYTE
T
SDA LINE
S
BUS ACTIVITY
A
C
K
DATA n
S
T
O
P
P
N
O
A
C
K
FIGURE 9-2: RANDOM READ
BUS ACTIVITY
MASTER
S
T
A
R
T
SDA LINE
S
BUS ACTIVITY
CONTROL
BYTE
WORD
ADDRESS (n)
A
C
K
S
T
A
R
T
S
A
C
K
CONTROL
BYTE
A
C
K
DATA (n)
S
T
O
P
P
N
O
A
C
K
© 1996 Microchip Technology Inc.
DS11183D-page 7

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