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24C08 데이터시트 PDF




MicrochipTechnology에서 제조한 전자 부품 24C08은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 24C08 기능
기능 8K/16K 5.0V I2C Serial EEPROMs
제조업체 MicrochipTechnology
로고 MicrochipTechnology 로고


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24C08 데이터시트, 핀배열, 회로
24C08B/16B
8K/16K 5.0V I2CSerial EEPROMs
FEATURES
• Single supply with operation from 4.5-5.5V
• Low power CMOS technology
- 1 mA active current typical
- 10 µA standby current typical at 5.5V
• Organized as 4 or 8 blocks of 256 bytes
(4 x 256 x 8) or (8 x 256 x 8)
• 2-wire serial interface bus, I2Ccompatible
• Schmitt trigger, filtered inputs for noise suppres-
sion
• Output slope control to eliminate ground bounce
• 100 kHz compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• ESD protection > 4,000V
• 1,000,000 ERASE/WRITE cycles guaranteed
• Data retention > 200 years
• 8-pin DIP, 8-lead or 14-lead SOIC packages
• Available for extended temperature range
- Automotive (E):
-40˚C to +125˚C
DESCRIPTION
The Microchip Technology Inc. 24C08B/16B is an 8K or
16K bit Electrically Erasable PROM intended for use in
extended/automotive temperature ranges. The device
is organized as four or eight blocks of 256 x 8-bit mem-
ory with a 2-wire serial interface. The 24C08B/16B also
has a page-write capability for up to 16 bytes of data.
The 24C08B/16B is available in the standard 8-pin DIP
and both 8-lead and 14-lead surface mount SOIC pack-
ages.
I2C is a trademark of Philips Corporation.
PACKAGE TYPES
PDIP
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
8-lead
SOIC
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
14-lead
SOIC
NC 1
A0 2
A1 3
NC 4
A2 5
VSS 6
NC 7
14 NC
13 VCC
12 WP
11 NC
10 SCL
9 SDA
8 NC
BLOCK DIAGRAM
WP
HV GENERATOR
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
XDEC
SDA SCL
EEPROM
ARRAY
PAGE LATCHES
YDEC
VCC SENSE AMP
VSS R/W CONTROL
© 1996 Microchip Technology Inc.
DS21081D-page 1
This document was created with FrameMaker 4 0 4




24C08 pdf, 반도체, 판매, 대치품
24C08B/16B
2.0 FUNCTIONAL DESCRIPTION
The 24C08B/16B supports a Bi-directional 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24C08B/16B
works as slave. Both, master and slave can operate as
transmitter or receiver but the master device deter-
mines which mode is activated.
3.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1 Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2 Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3 Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4 Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
3.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note:
The 24C08B/16B does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by NOT generating an acknowledge
bit on the last byte that has been clocked out of the
slave. In this case, the slave (24C08B/16B) will leave
the data line HIGH to enable the master to generate the
STOP condition.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A) (B) (D) (D)
SCL
(C) (A)
SDA
START
CONDITION
ADDRESS OR
DATA
ACKNOWLEDGE ALLOWED
VALID
TO CHANGE
STOP
CONDITION
DS21081D-page 4
© 1996 Microchip Technology Inc.

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24C08 전자부품, 판매, 대치품
24C08B/16B
FIGURE 7-1: CURRENT ADDRESS READ
BUS ACTIVITY
MASTER
S
T
A
R
T
CONTROL
BYTE
DATA n
S
T
O
P
SDA LINE
S
P
BUS ACTIVITY
AN
CO
K
A
C
K
FIGURE 7-2: RANDOM READ
BUS ACTIVITY
MASTER
S
T
A
R
T
SDA LINE
S
CONTROL
BYTE
BUS ACTIVITY
WORD
ADDRESS (n)
A
C
K
S
T
A
R
T
S
A
C
K
CONTROL
BYTE
A
C
K
DATA (n)
S
T
O
P
P
N
O
A
C
K
FIGURE 7-3: SEQUENTIAL READ
BUS ACTIVITY CONTROL
MASTER
BYTE
DATA n
DATA n + 1
DATA n + 2
DATA n + X
S
T
O
P
SDA LINE
AA A A
BUS ACTIVITY
C
C
C
C
KK K K
P
N
O
A
C
K
8.0 PIN DESCRIPTIONS
8.1 SDA Serial Address/Data Input/Output
This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to VCC (typical 10).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
8.2 SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
8.3 WP
This pin must be connected to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
(read/write the entire memory 000-7FF).
If tied to VCC, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.
This feature allows the user to use the 24C08B/16B as
a serial ROM when WP is enabled (tied to VCC).
8.4 A0, A1, A2
These pins are not used by the 24C08B/16B. They
may be left floating or tied to either VSS or VCC.
© 1996 Microchip Technology Inc.
DS21081D-page 7

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