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JS28F00AP30BFA 데이터시트 PDF




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부품번호 JS28F00AP30BFA 기능
기능 Micron Parallel NOR Flash Embedded Memory (P30-65nm)
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JS28F00AP30BFA 데이터시트, 핀배열, 회로
512Mb, 1Gb, 2Gb: P30-65nm
Features
Micron Parallel NOR Flash Embedded
Memory (P30-65nm)
JS28F512P30BFx, JS28F512P30EFx, JS28F512P30TFx,
PC28F512P30BFx, PC28F512P30EFx, PC28F512P30TFx
JS28F00AP30BFx, JS28F00AP30TFx, JS28F00AP30EFx,
PC28F00AP30BFx, PC28F00AP30TFx, PC28F00AP30EFx,
RC28F00AP30BFx, RC28F00AP30TFx, PC28F00BP30EFx
Features
• High performance
• Easy BGA package features
– 100ns initial access for 512Mb, 1Gb Easy BGA
– 105ns initial access for 2Gb Easy BGA
– 25ns 16-word asychronous page read mode
– 52 MHz (Easy BGA) with zero WAIT states and
17ns clock-to-data output synchronous burst
read mode
– 4-, 8-, 16-, and continuous word options for burst
mode
• TSOP package features
– 110ns initial access for 512Mb, 1Gb TSOP
• Both Easy BGA and TSOP package features
– Buffered enhanced factory programming (BEFP)
at 2 MB/s (TYP) using a 512-word buffer
– 1.8V buffered programming at 1.46 MB/s (TYP)
using a 512-word buffer
• Architecture
– MLC: highest density at lowest cost
– Symmetrically blocked architecture (512Mb, 1Gb,
2Gb)
– Asymmetrically blocked architecture (512Mb,
1Gb); four 32KB parameter blocks: top or bottom
configuration
– 128KB main blocks
– Blank check to verify an erased block
• Voltage and power
– VCC (core) voltage: 1.7–2.0V
– VCCQ (I/O) voltage: 1.7–3.6V
– Standy current: 70µA (TYP) for 512Mb; 75µA
(TYP) for 1Gb
– 52 MHz continuous synchronous read current:
21mA (TYP), 24mA (MAX)
• Security
– One-time programmable register: 64 OTP bits,
programmed with unique information from Mi-
cron; 2112 OTP bits available for customer pro-
gramming
– Absolute write protection: VPP = VSS
– Power-transition erase/program lockout
– Individual zero-latency block locking
– Individual block lock-down
– Password access
• Software
25μs (TYP) program suspend
25μs (TYP) erase suspend
– Flash Data Integrator optimized
– Basic command set and extended function Inter-
face (EFI) command set compatible
– Common flash interface
• Density and Packaging
– 56-lead TSOP package (512Mb, 1Gb)
– 64-ball Easy BGA package (512Mb, 1Gb, 2Gb)
– 16-bit wide data bus
• Quality and reliabilty
– JESD47 compliant
– Operating temperature: –40°C to +85°C
– Minimum 100,000 ERASE cycles per block
– 65nm process technology
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
http://www.Datasheet4U.com




JS28F00AP30BFA pdf, 반도체, 판매, 대치품
512Mb, 1Gb, 2Gb: P30-65nm
Features
End of Wordline Considerations .................................................................................................................. 41
WAIT Signal Polarity and Functionality ........................................................................................................ 42
WAIT Delay ................................................................................................................................................ 43
Burst Sequence .......................................................................................................................................... 43
Clock Edge ................................................................................................................................................. 44
Burst Wrap ................................................................................................................................................. 44
Burst Length .............................................................................................................................................. 44
One-Time Programmable Registers ................................................................................................................. 45
Read OTP Registers ..................................................................................................................................... 45
Program OTP Registers ............................................................................................................................... 46
Lock OTP Registers ..................................................................................................................................... 46
Common Flash Interface ................................................................................................................................ 48
READ CFI Structure Output ........................................................................................................................ 48
Flowcharts ..................................................................................................................................................... 62
Power and Reset Specifications ....................................................................................................................... 71
Power Supply Decoupling ........................................................................................................................... 72
Maximum Ratings and Operating Conditions .................................................................................................. 73
DC Electrical Specifications ............................................................................................................................ 74
AC Test Conditions and Capacitance ............................................................................................................... 76
AC Read Specifications ................................................................................................................................... 78
AC Write Specifications ................................................................................................................................... 85
Program and Erase Characteristics .................................................................................................................. 91
Revision History ............................................................................................................................................. 92
Rev. B – 12/13 ............................................................................................................................................. 92
Rev. A – 8/13 ............................................................................................................................................... 92
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
4 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.

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JS28F00AP30BFA 전자부품, 판매, 대치품
512Mb, 1Gb, 2Gb: P30-65nm
General Description
General Description
The Micron Parallel NOR Flash memory is the latest generation of Flash memory devi-
ces. Benefits include more density in less space, high-speed interface device, and sup-
port for code and data storage. Features include high-performance synchronous-burst
read mode, fast asynchronous access times, low power, flexible security options, and
three industry-standard package choices. The product family is manufactured using Mi-
cron 65nm process technology.
The NOR Flash device provides high performance at low voltage on a 16-bit data bus.
Individually erasable memory blocks are sized for optimum code and data storage.
Upon initial power up or return from reset, the device defaults to asynchronous page-
mode read. Configuring the read configuration register enables synchronous burst-
mode reads. In synchronous burst mode, output data is synchronized with a user-sup-
plied clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization.
In addition to the enhanced architecture and interface, the device incorporates technol-
ogy that enables fast factory PROGRAM and ERASE operations. Designed for low-volt-
age systems, the devIce supports READ operations with VCC at the low voltages, and
ERASE and PROGRAM operations with VPP at the low voltages or VPPH. Buffered en-
hanced factory programming (BEFP) provides the fastest Flash array programming per-
formance with VPP at VPPH, which increases factory throughput. With V PP at low voltag-
es, VCC and VPP can be tied together for a simple, ultra low-power design. In addition to
voltage flexibility, a dedicated VPP connection provides complete data protection when
VPP VPPLK.
A command user interface is the interface between the system processor and all inter-
nal operations of the device. The device automatically executes the algorithms and tim-
ings necessary for block erase and program. A status register indicates ERASE or PRO-
GRAM completion and any errors that may have occurred.
An industry-standard command sequence invokes program and erase automation.
Each ERASE operation erases one block. The erase suspend feature enables system soft-
ware to pause an ERASE cycle to read or program data in another block. Program sus-
pend enables system software to pause programming to read other locations. Data is
programmed in word increments (16 bits).
The protection register enables unique device identification that can be used to in-
crease system security. The individual block lock feature provides zero-latency block
locking and unlocking. The device includes enhanced protection via password access;
this new feature supports write and/or read access protection of user-defined blocks. In
addition, the device also provides the full-device OTP security feature.
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
7 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.

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JS28F00AP30BFA

Micron Parallel NOR Flash Embedded Memory (P30-65nm)

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Micron Parallel NOR Flash Embedded Memory (P30-65nm)

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