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BU4942 데이터시트 PDF : 부품 기능 및 핀배열

부품번호 BU4942
기능 Low Voltage Standard CMOS Voltage Detector IC Series
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BU4942 데이터시트 및 BU4942 PDF

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BU4942 pdf, 반도체, 판매, 대치품
BU48□□G, BU48□□F, BU48□□FVE, BU49□□G, BU49□□F, BU49□□FVE series Technical Note
Reference Data (Unless specified otherwise, Ta=25°C)
0.6
BU4816F
0.5
0.4
0.3
0.2
0.1
0.0
01
2 3 45
67
VDD SUPPLY VOLTAGE VDD [V]
Fig.3 Circuit Current
5
BU4816F
4
3
2 VDD=1.2V
1
0
0.0 0.5 1.0 1.5 2.0 2.5
DRAIN-SOURCE VOLTAGE VDS[V]
Fig.4 “LOW” Output Current
25
BU4916F
20 VDD=6.0V
15
VDD=4.8V
10
5
0
01
2 3 45
6
DRAIN-SOURCE VOLTAGE VDS[V]
Fig.5 “High” Output Current
7
BU4816F
6
5
4
3
2
1
0
01
2 3 45
67
VDD SUPPLY VOLTAGE VDD [V]
Fig.6 I/O Characteristics
0.5
BU4816F
0.4
0.3
0.2
0.1
0.0
-40
0 40 80 120
TEMPERATURE Ta[]
Fig.9 Circuit Current when ON
1.0
BU4816F
0.8
0.6
0.4
0.2
0.0
0.0 0.5 1.0 1.5 2.0 2.5
VDD SUPPLY VOLTAGE VDD [V]
Fig.7 Operating Limit Voltage
1.0
BU4816F
0.8
0.6
0.4
0.2
0.0
-40
0 40 80 120
TEMPERATURE Ta[]
Fig.10 Circuit Current when OFF
2.0
Low to high(VDET+ΔVDET)
1.5
High to low(VDET)
BU4816F
1.0
-40 0
40 80 120
TEMPERATURE Ta[]
Fig.8 Detecting Voltage
Release Voltage
1.0
BU4816F
0.8
0.6
0.4
0.2
0.0
-40
0 40 80 120
TEMPERATURE Ta[]
Fig.11 Operating Limit Voltage
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
4/8
2009.06 - Rev .C

4페이지

BU4942 전자부품, 판매, 대치품
BU48□□G, BU48□□F, BU48□□FVE, BU49□□G, BU49□□F, BU49□□FVE series Technical Note
Operation Notes
1 . Absolute maximum range
Absolute Maximum Ratings are those values beyond which the life of a device may be destroyed. We cannot be defined the
failure mode, such as short mode or open mode. Therefore a physical security countermeasure, like fuse, is to be given
when a specific mode to be beyond absolute maximum ratings is considered.
2 . GND potential
GND terminal should be a lowest voltage potential every state.
Please make sure all pins that are over ground even if include transient feature.
3 . Electrical Characteristics
Be sure to ch eck the el ectrical char acteristics, that are one the tent ative specif ication will b e cha nged b y temp erature,
supply voltage, and external circuit.
4 . Bypass Capacitor for Noise Rejection
Please put into the to reject noise between VDD pin and GND with 1uF over and between VOUT pin and GND with 1000pF.
If extremely big capacitor is used, transient response might be late. Please confirm sufficiently for the point.
5 . Short Circuit between Terminal and Soldering
Don’t short-circuit between Output pin and VDD pin, Output pin and GND pin, or VDD pin and GND pin. When soldering the
IC on circuit board please is unusually cautious about the orientation and the position of the IC. When the orientation is
mistaken the IC may be destroyed.
6 . Electroma gnetic Field
Mal-function may happen when the device is used in the strong electromagnetic field.
7 . The VDD line inpedance might cause oscillation because of the detection current.
8. A VDD -GND capacitor (as close connection as possible) should be used in high VDD line impedance condition.
9 . Lower than the mininum input voltage makes the VOUT high impedance, and it must be VDD in pull up (VDD) condition.
10. Recommended value of RL Resistar is over 10k(VDET=1.5V~4.8V),
over 100k(VDET=0.9~1.4V).
11. This IC has extremely high impedance terminals. Small leak current due to the uncleanness of PCB surface might cause
unexpected operations. Application values in these conditions should be selected carefully. If 10Mleakage is assumed
between the CT terminal and the GND terminal, 1Mconnection between the CT terminal and the VDD terminal would be
recommended. Also, if the leakage is assumed between the VOUT terminal and the GND terminal, the pull up resistor
should be less than 1/10 of the assumed leak resistance.
12. Ex ternal parameters
For RL, the recommended range is 10k~1M. There are many factors (board layout, etc) that can affect characteristics.
Please verify and confirm using practical applications.
13. Power on reset operation
Please note that the power on reset output varies with the Vcc rise up time. Please verify the actual operation.
14. Precautions for board inspection
Connecting low-impedance capacitors to run inspections with the board may produce stress on the IC. Therefore, be
certain to use proper discharge procedure before each process of the test operation.
To prevent electrostatic accumulation and discharge in the assembly process, thoroughly ground yourself and any
equipment that could sustain ESD damage, and continue observing ESD-prevention procedures in all handing, transfer
and storage operations. Before attempting to connect components to the test setup, make certain that the power supply is
OFF. Likewise, be sure the power supply is OFF before removing any component connected to the test setup.
15. W hen the po wer su pply, is turned on b ecause of ince rtain case s, moment ary Rash-current flo w i nto the IC at the log ic
unsettled, the couple capacitance, GND pattern of width and leading line must be considered.
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
7/8
2009.06 - Rev .C

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