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PDF ES8323 Data sheet ( Hoja de datos )
| Número de pieza | ES8323 | |
| Descripción | Low Power Stereo Audio CODEC | |
| Fabricantes | Everest Semiconductor | |
| Logotipo |  |
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ES8323
Low Power Stereo Audio CODEC
With Headphone Amplifier
GENERAL DESCRIPTION
ES8323 is a high performance, low
power and low cost audio CODEC.
It consists of 2-ch ADC, 2-ch DAC,
microphone amplifier, headphone
amplifier, digital sound effects, and
analog mixing and gain functions.
The device uses advanced multi-bit
delta-sigma modulation technique
to convert data between digital and
analog. The multi-bit delta-sigma
modulators make the device with
low sensitivity to clock jitter and low
out of band noise.
APPLICATIONS
• MID
• MP3, MP4, PMP
• Wireless audio
• Digital camera, camcorder
• GPS
• Bluetooth
• Portable audio devices
FEATURES
ADC
• 24-bit, 8 kHz to 96 kHz sampling frequency
• 95 dB dynamic range, 95 dB signal to noise ratio,
-85 dB THD+N
• Stereo or mono microphone interface with
microphone amplifier
• Auto level control and noise gate
• 2-to-1 analog input selection
• Various analog input mixing and gains
DAC
• 24-bit, 8 kHz to 96 kHz sampling frequency
• 96 dB dynamic range, 96 dB signal to noise ratio,
-83 dB THD+N
• 40 mW headphone amplifier, pop noise free,
capless option
• Stereo enhancement
• Bass and Treble
• Various analog output mixing and gains
Low Power
• 1.8V to 3.3V operation
• 7 mW playback; 16 mW playback and record
System
• I2C or SPI uC interface
• 256Fs, 384Fs, USB 12 MHz or 24 MHz
• Master or slave serial port
• I2S, Left Justified, DSP/PCM Mode
ORDERING INFORMATION
ES8323 -40°C ~ +85°C
QFN-28
Revision 1.0
1
April 2011
http://www.Datasheet4U.com
1 page  
Everest Semiconductor
2 28-PIN QFN AND PIN DESCRIPTIONS
ES8323
MCLK 1
DVDD 2
PVDD 3
DGND 4
SCLK 5
DSDIN 6
LRCK 7
21 RIN1
20 VMID
19 DACVREF
18 AGND
17 AVDD
16 HPVDD
15 LOUT1
Revision 1.0
5
April 2011
5 Page 
Everest Semiconductor
difference from the I2C protocol.
ES8323
Table 3 Write Data to Register in 2-wire Interface Mode
Chip Address R /W R egister Address D ata to be written
001000 AD0 0 ACK
RAM
ACK
DATA
Table 4 Read Data from Register in 2-wire Interface Mode
Chip Address R /W R egister Address
001000 AD0 0 ACK
RAM
Chip Address R /W D ata to be read
001000 AD0 1 ACK
DATA
6 CONFIGURATION REGISTER DEFINITION
SPI and 2-wire configuration interface share the same registers because there
is only one i nterface act ive at any time. Ther e ar e t otal of 53 u ser
programmable 8 -bit r egisters in t his device. These r egisters co ntrol t he
operations of A DC and DAC. E xternal m aster co ntroller ca n a ccess these
registers by using the slave address specified in RAM (Register Address Map)
register as shown in the Table 5.
Table 5 Bit Content of Register Address Map
B7 B6 B5 B4 B3
B2 B1 B0
Reg. 00 SCPReset
LRCM
DACMCLK
SameFs
SeqEn
EnRef
VMIDSEL
Reg. 01
LPVcmMod LPVrefBuf
PdnAna
PdnIbiasgen
VrefrLo PdnVrefbuf
Reg. 02 adc_DigPDN dac_DigPDN adc_stm_rst dac_stm_rst ADCDLL_PDN DACDLL_PDN adcVref_PDN dacVref_PDN
Reg. 03 PdnAINL
PdnAINR
PdnADCL PdnADCR
PdnMICB PdnADCBiasgen flashLP
int1LP
Reg. 04 PdnDACL
PdnDACR
LOUT1
ROUT1
Reg. 05 LPDACL
LPDACR
LPLOUT1
Reg. 06 LPPGA
LPLMIX
LPADCvrp LPDACvrp
Reg. 07
VSEL
Reg. 08
MSC
MCLKDIV2 BCLK_INV
BCLKDIV
Reg. 09
MicAmpL
MicAmpR
Reg. 10
LINSEL
RINSEL
DSSEL
DSR
Reg. 11
DS
MONOMIX
TRI
Reg. 12
DATSEL
ADCLRP
ADCWL
ADCFORMAT
Reg. 13
ADCFsMode
ADCFsRatio
Reg. 14 ADC_invL
ADC_invR ADC_HPF_L ADC_HPF_R
Reg. 15 ADCRampRate ADCSoftRamp
ADCLeR
ADCMute
Reg. 16
LADCVOL
Reg. 17
RADCVOL
Reg. 18
ALCSEL
MAXGAIN
MINGAIN
Reg. 19
ALCLVL
ALCHLD
Revision 1.0
11
April 2011
11 Page | ||
| Páginas | Total 34 Páginas | |
| PDF Descargar | [ Datasheet ES8323.PDF ] | |
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